The functions of copy_ports and connect_ports are improved.

Author: shtaxxx

tests/core/instance_/multiple_instances/Makefile

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+TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py *.out tmp.v uut.vcd

tests/core/instance_/multiple_instances/multiple_instances.py

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+from __future__ import absolute_import
+from __future__ import print_function
+import sys
+import os
+import collections
+
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
+
+from veriloggen import *
+
+def mkLed():
+    m = Module('blinkled')
+    width = m.Parameter('WIDTH', 8)
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+    led = m.OutputReg('LED', width)
+    count = m.Reg('count', 32)
+
+    m.Always(Posedge(clk))(
+        If(rst)(
+            count(0)
+        ).Else(
+            If(count == 1023)(
+                count(0)
+            ).Else(
+                count(count + 1)
+            )
+        ))
+    
+    m.Always(Posedge(clk))(
+        If(rst)(
+            led( 0 )
+        ).Else(
+            If(count == 1023)(
+                led( led + 1 )
+            )
+        ))
+
+    return m
+
+def mkTop():
+    m = Module('top')
+    led = mkLed()
+
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+    
+    params = m.copy_params(led, prefix='A_')
+    ports = m.copy_ports(led, prefix='A_', exclude=('CLK', 'RST'))
+    
+    params = m.copy_params(led, prefix='B_')
+    ports = m.copy_ports(led, prefix='B_', exclude=('CLK', 'RST'))
+    
+    m.Instance(led, 'inst_blinkled_a',
+               m.connect_params(led, prefix='A_'),
+               m.connect_ports(led, prefix='') + m.connect_ports(led, prefix='A_'))
+               
+    
+    m.Instance(led, 'inst_blinkled_b',
+               m.connect_params(led, prefix='B_'),
+               m.connect_ports(led, prefix='') + m.connect_ports(led, prefix='B_'))
+
+    return m
+
+if __name__ == '__main__':
+    top = mkTop()
+    verilog = top.to_verilog()
+    print(verilog)

tests/core/instance_/multiple_instances/test_multiple_instances.py

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+from __future__ import absolute_import
+from __future__ import print_function
+import multiple_instances
+
+expected_verilog = """
+module top #
+(
+  parameter A_WIDTH = 8,
+  parameter B_WIDTH = 8
+)
+(
+  input CLK,
+  input RST,
+  output [A_WIDTH-1:0] A_LED,
+  output [B_WIDTH-1:0] B_LED
+);
+
+  blinkled
+  #(
+    .WIDTH(A_WIDTH)
+  )
+  inst_blinkled_a
+  (
+    .CLK(CLK),
+    .RST(RST),
+    .LED(A_LED)
+  );
+
+  blinkled
+  #(
+    .WIDTH(B_WIDTH)
+  )
+  inst_blinkled_b
+  (
+    .CLK(CLK),
+    .RST(RST),
+    .LED(B_LED)
+  );
+
+endmodule
+
+module blinkled #
+(
+  parameter WIDTH = 8
+)
+(
+  input CLK,
+  input RST,
+  output reg [WIDTH-1:0] LED
+);
+
+  reg [32-1:0] count;
+
+  always @(posedge CLK) begin
+    if(RST) begin
+      count <= 0;
+    end else begin
+      if(count == 1023) begin
+        count <= 0;
+      end else begin
+        count <= count + 1;
+      end
+    end
+  end
+
+  always @(posedge CLK) begin
+    if(RST) begin
+      LED <= 0;
+    end else begin
+      if(count == 1023) begin
+        LED <= LED + 1;
+      end 
+    end
+  end
+
+endmodule
+"""
+
+def test_led():
+    test_module = multiple_instances.mkTop()
+    code = test_module.to_verilog()
+
+    from pyverilog.vparser.parser import VerilogParser
+    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
+    parser = VerilogParser()
+    expected_ast = parser.parse(expected_verilog)
+    codegen = ASTCodeGenerator()
+    expected_code = codegen.visit(expected_ast)
+
+    assert(expected_code == code)