Bug fix: A bug of AXI-slave interface that dismisses one of simultaneous read/write requests is fixed.

Author: shtaxxx

examples/thread_add_ipxact/test_thread_add_ipxact.py

@@ -700,8 +700,8 @@
   reg _tmp_2;
   reg _tmp_3;
   reg _tmp_4;
-  assign saxi_awready = (_saxi_register_fsm == 0) && !_tmp_1 && !_tmp_2 && !saxi_bvalid && _tmp_3;
-  assign saxi_arready = (_saxi_register_fsm == 0) && !_tmp_2 && !_tmp_1 && _tmp_4;
+  assign saxi_awready = (_saxi_register_fsm == 0) && (!_tmp_1 && !_tmp_2 && !saxi_bvalid && _tmp_3);
+  assign saxi_arready = (_saxi_register_fsm == 0) && (!_tmp_2 && !_tmp_1 && _tmp_4 && !_tmp_3);
   reg [_saxi_maskwidth-1:0] _tmp_5;
   wire signed [32-1:0] _tmp_6;
   assign _tmp_6 = (_tmp_5 == 0)? _saxi_register_0 : 

examples/thread_embedded_verilog_ipcore/test_thread_embedded_verilog_ipxact.py

@@ -1258,8 +1258,8 @@
   reg _tmp_2;
   reg _tmp_3;
   reg _tmp_4;
-  assign saxi_awready = (_saxi_register_fsm == 0) && !_tmp_1 && !_tmp_2 && !saxi_bvalid && _tmp_3;
-  assign saxi_arready = (_saxi_register_fsm == 0) && !_tmp_2 && !_tmp_1 && _tmp_4;
+  assign saxi_awready = (_saxi_register_fsm == 0) && (!_tmp_1 && !_tmp_2 && !saxi_bvalid && _tmp_3);
+  assign saxi_arready = (_saxi_register_fsm == 0) && (!_tmp_2 && !_tmp_1 && _tmp_4 && !_tmp_3);
   reg [_saxi_maskwidth-1:0] _tmp_5;
   wire signed [32-1:0] _tmp_6;
   assign _tmp_6 = (_tmp_5 == 0)? _saxi_register_0 : 

examples/thread_ipxact/test_thread_ipxact.py

@@ -641,8 +641,8 @@
   reg _tmp_2;
   reg _tmp_3;
   reg _tmp_4;
-  assign saxi_awready = (_saxi_register_fsm == 0) && !_tmp_1 && !_tmp_2 && !saxi_bvalid && _tmp_3;
-  assign saxi_arready = (_saxi_register_fsm == 0) && !_tmp_2 && !_tmp_1 && _tmp_4;
+  assign saxi_awready = (_saxi_register_fsm == 0) && (!_tmp_1 && !_tmp_2 && !saxi_bvalid && _tmp_3);
+  assign saxi_arready = (_saxi_register_fsm == 0) && (!_tmp_2 && !_tmp_1 && _tmp_4 && !_tmp_3);
   reg [_saxi_maskwidth-1:0] _tmp_5;
   wire signed [32-1:0] _tmp_6;
   assign _tmp_6 = (_tmp_5 == 0)? _saxi_register_0 : 

examples/thread_memcpy_ipxact/test_thread_memcpy_ipxact.py

@@ -1255,8 +1255,8 @@
   reg _tmp_2;
   reg _tmp_3;
   reg _tmp_4;
-  assign saxi_awready = (_saxi_register_fsm == 0) && !_tmp_1 && !_tmp_2 && !saxi_bvalid && _tmp_3;
-  assign saxi_arready = (_saxi_register_fsm == 0) && !_tmp_2 && !_tmp_1 && _tmp_4;
+  assign saxi_awready = (_saxi_register_fsm == 0) && (!_tmp_1 && !_tmp_2 && !saxi_bvalid && _tmp_3);
+  assign saxi_arready = (_saxi_register_fsm == 0) && (!_tmp_2 && !_tmp_1 && _tmp_4 && !_tmp_3);
   reg [_saxi_maskwidth-1:0] _tmp_5;
   wire signed [32-1:0] _tmp_6;
   assign _tmp_6 = (_tmp_5 == 0)? _saxi_register_0 : 

examples/thread_verilog_submodule_ipxact/test_thread_verilog_submodule_ipxact.py

@@ -1266,8 +1266,8 @@
   reg _tmp_2;
   reg _tmp_3;
   reg _tmp_4;
-  assign saxi_awready = (_saxi_register_fsm == 0) && !_tmp_1 && !_tmp_2 && !saxi_bvalid && _tmp_3;
-  assign saxi_arready = (_saxi_register_fsm == 0) && !_tmp_2 && !_tmp_1 && _tmp_4;
+  assign saxi_awready = (_saxi_register_fsm == 0) && (!_tmp_1 && !_tmp_2 && !saxi_bvalid && _tmp_3);
+  assign saxi_arready = (_saxi_register_fsm == 0) && (!_tmp_2 && !_tmp_1 && _tmp_4 && !_tmp_3);
   reg [_saxi_maskwidth-1:0] _tmp_5;
   wire signed [32-1:0] _tmp_6;
   assign _tmp_6 = (_tmp_5 == 0)? _saxi_register_0 : 

tests/extension/types_/axi_/slave_readwrite/test_types_axi_slave_readwrite.py

@@ -672,8 +672,8 @@
   reg _tmp_3;
   reg _tmp_4;
   reg _tmp_5;
-  assign myaxi_awready = (fsm == 0) && !_tmp_2 && !_tmp_3 && !myaxi_bvalid && _tmp_4;
-  assign myaxi_arready = (fsm == 0) && !_tmp_3 && !_tmp_2 && _tmp_5;
+  assign myaxi_awready = (fsm == 0) && (!_tmp_2 && !_tmp_3 && !myaxi_bvalid && _tmp_4);
+  assign myaxi_arready = (fsm == 0) && (!_tmp_3 && !_tmp_2 && _tmp_5 && !_tmp_4);
   reg [32-1:0] rdata;
   reg _myaxi_cond_0_1;
   assign myaxi_wready = fsm == 100;

tests/extension/types_/axi_/slave_readwrite_lite/test_types_axi_slave_readwrite_lite.py

@@ -485,8 +485,8 @@
   reg _tmp_2;
   reg _tmp_3;
   reg _tmp_4;
-  assign myaxi_awready = (fsm == 0) && !_tmp_1 && !_tmp_2 && !myaxi_bvalid && _tmp_3;
-  assign myaxi_arready = (fsm == 0) && !_tmp_2 && !_tmp_1 && _tmp_4;
+  assign myaxi_awready = (fsm == 0) && (!_tmp_1 && !_tmp_2 && !myaxi_bvalid && _tmp_3);
+  assign myaxi_arready = (fsm == 0) && (!_tmp_2 && !_tmp_1 && _tmp_4 && !_tmp_3);
   reg [32-1:0] rdata;
   reg _myaxi_cond_0_1;
   assign myaxi_wready = fsm == 100;

veriloggen/types/axi.py

@@ -1551,16 +1551,17 @@ def pull_request_counter(self, cond, counter=None):
             prev_arvalid(self.raddr.arvalid)
         )
 
-        writeval = (vtypes.Ands(vtypes.Not(writevalid), vtypes.Not(readvalid),
-                                vtypes.Not(self.wresp.bvalid),
-                                prev_awvalid) if ready is None else
-                    vtypes.Ands(ready, vtypes.Not(writevalid), vtypes.Not(readvalid),
-                                vtypes.Not(self.wresp.bvalid),
-                                prev_awvalid))
-        readval = (vtypes.Ands(vtypes.Not(readvalid), vtypes.Not(writevalid),
-                               prev_arvalid) if ready is None else
-                   vtypes.Ands(ready, vtypes.Not(readvalid), vtypes.Not(writevalid),
-                               prev_arvalid))
+        writeval = vtypes.Ands(vtypes.Not(writevalid), vtypes.Not(readvalid),
+                               vtypes.Not(self.wresp.bvalid),
+                               prev_awvalid)
+        if ready is not None:
+            writeval = vtypes.Ands(ready, writeval)
+
+        readval = vtypes.Ands(vtypes.Not(readvalid), vtypes.Not(writevalid),
+                              prev_arvalid, vtypes.Not(prev_awvalid))
+
+        if ready is not None:
+            readval = vtypes.Ands(ready, readval)
 
         _connect_ready(self.waddr.awready._get_module(),
                        self.waddr.awready, writeval)
@@ -2094,16 +2095,17 @@ def pull_request(self, cond):
             prev_arvalid(self.raddr.arvalid)
         )
 
-        writeval = (vtypes.Ands(vtypes.Not(writevalid), vtypes.Not(readvalid),
-                                vtypes.Not(self.wresp.bvalid),
-                                prev_awvalid) if ready is None else
-                    vtypes.Ands(ready, vtypes.Not(writevalid), vtypes.Not(readvalid),
-                                vtypes.Not(self.wresp.bvalid),
-                                prev_awvalid))
-        readval = (vtypes.Ands(vtypes.Not(readvalid), vtypes.Not(writevalid),
-                               prev_arvalid) if ready is None else
-                   vtypes.Ands(ready, vtypes.Not(readvalid), vtypes.Not(writevalid),
-                               prev_arvalid))
+        writeval = vtypes.Ands(vtypes.Not(writevalid), vtypes.Not(readvalid),
+                               vtypes.Not(self.wresp.bvalid),
+                               prev_awvalid)
+        if ready is not None:
+            writeval = vtypes.Ands(ready, writeval)
+
+        readval = vtypes.Ands(vtypes.Not(readvalid), vtypes.Not(writevalid),
+                              prev_arvalid, vtypes.Not(prev_awvalid))
+
+        if ready is not None:
+            readval = vtypes.Ands(ready, readval)
 
         _connect_ready(self.waddr.awready._get_module(),
                        self.waddr.awready, writeval)