change reset detection method for issue#14

Author: fukatani

pyverilog/dataflow/bindvisitor.py

@@ -229,10 +229,10 @@ def visit_Always(self, node):
 
         (clock_name, clock_edge, clock_bit,
          reset_name, reset_edge, reset_bit,
-         senslist) = self._createAlwaysinfo(node, current)
+         senslist, load_const_dict) = self._createAlwaysinfo(node, current)
 
         self.frames.setAlwaysInfo(clock_name, clock_edge, clock_bit,
-                                  reset_name, reset_edge, reset_bit, senslist)
+                                  reset_name, reset_edge, reset_bit, senslist, load_const_dict)
 
         self.generic_visit(node)
         self.frames.setCurrent(current)
@@ -255,11 +255,13 @@ def _createAlwaysinfo(self, node, scope):
         reset_edge = None
         reset_name = None
         reset_bit = None
+        reset_sig = None
+        is_sync_reset = True
+        r_finder = self.reset_finder(node, self.frames.current, self.dataflow)
 
-        #TODO unimplemented
-        #print('load: ' + str(self._first_lvalue_is_const(node)))
-        #print('if_branch: ' + str(self._has_if_branch(node)))
-        #print('reset_info: ' + str(self._get_rst_info(node)))
+        if str(r_finder._has_if_branch(node)) and any(r_finder.load_const_dict.values()):
+            reset_sig, reset_edge, reset_bit = r_finder.get_rst_info()
+            reset_name = self.searchTerminal(reset_sig, scope)
 
         for l in node.sens_list.list:
             if l.sig is None:
@@ -270,14 +272,16 @@ def _createAlwaysinfo(self, node, scope):
             else:
                 signame = self._get_signal_name(l.sig)
                 bit = 0
-            if signaltype.isClock(signame):
+
+            if signame == reset_sig and bit == reset_bit:
+                if l.type == reset_edge:
+                    is_sync_reset = False
+                else:
+                    raise verror.FormatError('Illegal reset polarity')
+            elif not clock_name: #First signal which is not reset is regard as clock.
                 clock_name = self.searchTerminal(signame, scope)
                 clock_edge = l.type
                 clock_bit = bit
-            elif signaltype.isReset(signame):
-                reset_name = self.searchTerminal(signame, scope)
-                reset_edge = l.type
-                reset_bit = bit
             else:
                 senslist.append(l)
 
@@ -286,135 +290,10 @@ def _createAlwaysinfo(self, node, scope):
         if reset_edge is not None and len(senslist) > 0:
             raise verror.FormatError('Illegal sensitivity list')
 
-        return (clock_name, clock_edge, clock_bit, reset_name, reset_edge, reset_bit, senslist)
-
-    #TODO This function is implemented for https://github.com/PyHDI/Pyverilog/issues/14.
-    #Be incorporated into formally in lator commit.
-    def _first_lvalue_is_const(self, node):
-        """ [FUNCTIONS]
-        Walk until lvalue and judge whether it is constant or not.
-
-        ex.
-        if(RST)
-          reg1 <= 1'd0: //const: judged as rst branch
-
-        if(RST)
-          reg1 <= {1'd0, 1'd0}: //const: judged as rst branch
-
-        if(RST)
-          reg1 <= reg2: //variable: judged as not rst branch
-
-        if(RST)
-          reg1 <= {1'd0, reg2}: //variable: judged as not rst branch
-        """
-        if isinstance(node, Always):
-            return self._first_lvalue_is_const(node.statement)
-        elif isinstance(node, Block):
-            return self._first_lvalue_is_const(node.statements[0])
-        elif isinstance(node, IfStatement):
-            return self._first_lvalue_is_const(node.true_statement)
-        elif isinstance(node, NonblockingSubstitution):
-            print(node.left.var)# for debug
-            return self._first_lvalue_is_const(node.right)
-        elif isinstance(node, Identifier):
-            node_chain = self.get_scopechain(node)
-            if node_chain in self.dataflow.terms.keys():
-                #Parameter is regard as constant.
-                return 'Parameter' in self.dataflow.terms[node_chain].termtype
-            return False
-        elif hasattr(node, 'children'):
-            for child in node.children():
-                if not self._first_lvalue_is_const(child):
-                    return False
-            return True
-        elif isinstance(node, Rvalue):
-            return self._first_lvalue_is_const(node.var)
-        elif hasattr(node, 'value'):
-            return True
-        else:
-            raise Exception('Pyverilog unknown error')
-
-    def get_scopechain(self, node):
-        assert isinstance(node, Identifier), 'Node type should be Identifier.'
-        scope_list = self.frames.current.get_module_list() + [util.ScopeLabel(str(node)),]
-        return util.ScopeChain(scope_list)
-
-    #TODO This function is implemented for https://github.com/PyHDI/Pyverilog/issues/14.
-    #Be incorporated into formally in lator commit.
-    def _get_rst_info(self, node, rst_name='', is_posedge=True, rst_bit=0):
-        """ [FUNCTIONS]
-        get reset information from first if statement.
-
-        ex1.
-        always @(posedge CLK or posedge RST) begin
-            if(RST)
-                reg1 <= 0;
-            else
-                reg1 <= !reg1;
-        end
-        ->RST is posedge RST.
-
-        ex2.
-        always @(posedge CLK or posedge RST) begin
-            if(!RSTN[1])
-                reg1 <= 0;
-            else
-                reg1 <= !reg1;
-        end
-        ->RSTN[1] is negedge RST.
-
-        ex3.
-        always @(posedge CLK or posedge RST) begin
-            if(RST && RST2)
-                reg1 <= 0;
-            else
-                reg1 <= !reg1;
-        end
-        -> reg1 has no reset. (too complex condition)
-        """
-        if isinstance(node, Always):
-            return self._get_rst_info(node.statement, rst_name, is_posedge, rst_bit)
-        elif isinstance(node, Block):
-            return self._get_rst_info(node.statements[0], rst_name, is_posedge, rst_bit)
-        elif isinstance(node, IfStatement):
-            return self._get_rst_info(node.cond, rst_name, is_posedge, rst_bit)
-        elif isinstance(node, pyverilog.vparser.ast.Ulnot):
-            is_posedge = not is_posedge
-            return self._get_rst_info(node.children()[0], rst_name, is_posedge, rst_bit)
-        elif isinstance(node, pyverilog.vparser.ast.Pointer):
-            #TODO if identifier
-            if isinstance(node.ptr, Identifier):
-                ptr_chain = self.get_scopechain(node.ptr)
-                if 'Parameter' in self.dataflow.terms[ptr_chain].termtype:
-                    rst_bit = self.dataflow.binddict[ptr_chain][0].tree.eval()
-                    return self._get_rst_info(node.var, rst_name, is_posedge, rst_bit)
-                else:
-                    return (None, None, None)
-            elif hasattr(node.ptr, 'value'):
-                return self._get_rst_info(node.var, rst_name, is_posedge, int(node.ptr.value))
-        elif isinstance(node, pyverilog.vparser.ast.Identifier):
-            return (node, is_posedge, rst_bit)
-        return (None, None, None)
-
-    #TODO This function is implemented for https://github.com/PyHDI/Pyverilog/issues/14.
-    #Be incorporated into formally in lator commit.
-    def _has_if_branch(self, node):
-        """ [FUNCTIONS]
-        Return always block have 'if branch' or not.
-        ex.
-        always @(posedge CLK or posedge RST) begin
-            reg1 <= 0;
-        end
-        -> reg1 has no reset. (If statement isn't exists.)
-        """
-        if isinstance(node, Always):
-            return self._has_if_branch(node.statement)
-        elif isinstance(node, Block):
-            return self._has_if_branch(node.statements[0])
-        elif isinstance(node, IfStatement):
-            return True
-        else:
-            return  False
+        if is_sync_reset:
+            reset_edge = 'sync'
+        return (clock_name, clock_edge, clock_bit, reset_name, reset_edge, reset_bit,
+                senslist, r_finder.load_const_dict)
 
     def visit_IfStatement(self, node):
         if self.frames.isFunctiondef() and not self.frames.isFunctioncall(): return
@@ -495,7 +374,6 @@ def visit_CaseStatement(self, node):
         start_frame = self.frames.getCurrent()
         caseframes = []
         self._case(node.comp, node.caselist, caseframes)
-        #self._case(node.comp, tuple(reversed(list(node.caselist))), caseframes)
         self.frames.setCurrent(start_frame)
         for f in caseframes:
             self.copyBlockingAssigns(f, start_frame)
@@ -662,15 +540,15 @@ def visit_Assign(self, node):
         self.addBind(node.left, node.right, bindtype='assign')
 
     def visit_BlockingSubstitution(self, node):
-        self.addBind(node.left, node.right, self.frames.getAlwaysStatus(), 'blocking')
+        self.addBind(node.left, node.right, self.frames.getAlwaysStatus(node.left), 'blocking')
 
     def visit_NonblockingSubstitution(self, node):
         if self.frames.isForpre() or self.frames.isForpost():
             raise verror.FormatError(("Non Blocking Substitution is not allowed"
                                       "in for-statement"))
         if self.frames.isFunctioncall():
             raise verror.FormatError("Non Blocking Substitution is not allowed in function")
-        self.addBind(node.left, node.right, self.frames.getAlwaysStatus(), 'nonblocking')
+        self.addBind(node.left, node.right, self.frames.getAlwaysStatus(node.left), 'nonblocking')
 
     def visit_SystemCall(self, node):
         print("Warning: Isolated system call is not supported: %s" % node.syscall)
@@ -1646,3 +1524,147 @@ def appendBranchTree(self, base, pos, tree):
                 base.condnode,
                 base.truenode,
                 self.appendBranchTree(base.falsenode, pos[1:], tree))
+
+    class reset_finder(object):
+        def __init__(self, node, current, dataflow):
+            self.current = current
+            self.dataflow = dataflow
+            self.is_posedge = 'posedge'
+            self.rst_bit = 0
+            self.rst_name = None
+            self.load_const_dict = {}
+            self._walk_in_first_ifbranch(node)
+            self._make_rst_info(node)
+
+        def _walk_in_first_ifbranch(self, node):
+            """ [FUNCTIONS]
+            Walk until lvalue and judge whether it is constant or not.
+
+            ex.
+            if(RST)
+              reg1 <= 1'd0: //const: judged as rst branch
+
+            if(RST)
+              reg1 <= {1'd0, 1'd0}: //const: judged as rst branch
+
+            if(RST)
+              reg1 <= reg2: //variable: judged as not rst branch
+
+            if(RST)
+              reg1 <= {1'd0, reg2}: //variable: judged as not rst branch
+            """
+            if isinstance(node, Always):
+                self._walk_in_first_ifbranch(node.statement)
+            elif isinstance(node, Block):
+                for statement in node.statements:
+                    self._walk_in_first_ifbranch(statement)
+            elif isinstance(node, IfStatement):
+                self._walk_in_first_ifbranch(node.true_statement)
+            elif isinstance(node, NonblockingSubstitution):
+                self.load_const_dict[node.left] = self.is_const(node.right)
+            else:
+                raise Exception('Pyverilog unknown error')
+
+        def is_const(self, node):
+            if isinstance(node, Identifier):
+                node_chain = self.get_scopechain(node)
+                if node_chain in self.dataflow.terms.keys():
+                    #Parameter is regard as constant.
+                    return 'Parameter' in self.dataflow.terms[node_chain].termtype
+            elif hasattr(node, 'children'):
+                for child in node.children():
+                    if not self.is_const(child):
+                        return False
+                else:
+                    return True
+            elif isinstance(node, Rvalue):
+                self.is_const(node.var)
+            elif hasattr(node, 'value'):
+                return True
+            else:
+                raise Exception('Pyverilog unknown error')
+
+        def get_is_const_subed(self):
+            return self.const_substituted
+
+        def get_scopechain(self, node):
+            assert isinstance(node, Identifier), 'Node type should be Identifier.'
+            scope_list = self.current.get_module_list() + [util.ScopeLabel(str(node)),]
+            return util.ScopeChain(scope_list)
+
+        def _make_rst_info(self, node):
+            """ [FUNCTIONS]
+            get reset information from first if statement.
+
+            ex1.
+            always @(posedge CLK or posedge RST) begin
+                if(RST)
+                    reg1 <= 0;
+                else
+                    reg1 <= !reg1;
+            end
+            ->RST is posedge RST.
+
+            ex2.
+            always @(posedge CLK or posedge RST) begin
+                if(!RSTN[1])
+                    reg1 <= 0;
+                else
+                    reg1 <= !reg1;
+            end
+            ->RSTN[1] is negedge RST.
+
+            ex3.
+            always @(posedge CLK or posedge RST) begin
+                if(RST && RST2)
+                    reg1 <= 0;
+                else
+                    reg1 <= !reg1;
+            end
+            -> reg1 has no reset. (too complex condition)
+            """
+            if isinstance(node, Always):
+                self._make_rst_info(node.statement)
+            elif isinstance(node, Block):
+                self._make_rst_info(node.statements[0])
+            elif isinstance(node, IfStatement):
+                self._make_rst_info(node.cond)
+            elif isinstance(node, Ulnot):
+                self.is_posedge = 'negedge' if self.is_posedge == 'posedge' else 'posedge'
+                self._make_rst_info(node.children()[0])
+            elif isinstance(node, Pointer):
+                if isinstance(node.ptr, Identifier):
+                    ptr_chain = self.get_scopechain(node.ptr)
+                    if 'Parameter' in self.dataflow.terms[ptr_chain].termtype:
+                        self.rst_bit = self.dataflow.binddict[ptr_chain][0].tree.eval()
+                        self._make_rst_info(node.var)
+                    else:
+                        self.is_posedge = None
+                        self.rst_name = None
+                        self.rst_bit = None
+                elif hasattr(node.ptr, 'value'):
+                    self.rst_bit = int(node.ptr.value)
+                    self._make_rst_info(node.var)
+            elif isinstance(node, pyverilog.vparser.ast.Identifier):
+                self.rst_name = str(node)
+
+        def _has_if_branch(self, node):
+            """ [FUNCTIONS]
+            Return always block have 'if branch' or not.
+            ex.
+            always @(posedge CLK or posedge RST) begin
+                reg1 <= 0;
+            end
+            -> reg1 has no reset. (If statement isn't exists.)
+            """
+            if isinstance(node, Always):
+                return self._has_if_branch(node.statement)
+            elif isinstance(node, Block):
+                return self._has_if_branch(node.statements[0])
+            elif isinstance(node, IfStatement):
+                return True
+            else:
+                return False
+
+        def get_rst_info(self):
+            return self.rst_name, self.is_posedge, self.rst_bit