tests has been rearranged. Symbolic links to pyverilog have been removed.

shtaxxx · shtaxxx · commit f692ad08e47d · 2015-10-29T16:45:39.000+09:00
diff --git a/Makefile b/Makefile
@@ -5,6 +5,7 @@ all:
 .PHONY: clean
 clean:
 	make clean -C ./pyverilog
+	make clean -C ./tests
 	rm -rf *.pyc __pycache__ *.out parsetab.py pyverilog.egg-info build dist
 
 .PHONY: release
diff --git a/tests/Makefile b/tests/Makefile
@@ -1,10 +1,14 @@
+PYTHON=python3
+#PYTHON=python
+
 .PHONY: all
 all: clean
 
 .PHONY: test
 test:
-	find . -maxdepth 1 -type d |grep "./" | xargs -I {} make test -C {} 
+	$(PYTHON) -m pytest -vv
 
 .PHONY: clean
 clean:
-	find . -maxdepth 1 -type d |grep "./" | xargs -I {} make clean -C {} 
+	rm -rf *.pyc __pycache__ parsetab.py *.out .cache
+	find . -maxdepth 1 -type d |grep "./" | xargs -I {} make clean -C {}
diff --git a/tests/ast_code_generator_test/Makefile b/tests/ast_code_generator_test/Makefile
@@ -1,19 +1,13 @@
-TEST=*.py
-ARGS=
-
 PYTHON=python3
 #PYTHON=python
-#OPT=-m pdb
-#OPT=-m cProfile -s time
-#OPT=-m cProfile -o profile.rslt
 
 .PHONY: all
-all: test
+all: clean
 
 .PHONY: test
 test:
-	$(PYTHON) -m pytest -vv $(TEST)
+	$(PYTHON) -m pytest -vv
 
 .PHONY: clean
 clean:
-	rm -rf *.pyc __pycache__ parsetab.py *.out
+	rm -rf *.pyc __pycache__ parsetab.py *.out .cache
diff --git a/tests/ast_code_generator_test/pyverilog b/tests/ast_code_generator_test/pyverilog
diff --git a/tests/ast_code_generator_test/test_ast_assign.py b/tests/ast_code_generator_test/test_ast_assign.py
@@ -1,5 +1,6 @@
 import os
 import sys
+
 import pyverilog.vparser.ast as vast
 from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
 
diff --git a/tests/dataflow_test/Makefile b/tests/dataflow_test/Makefile
@@ -1,19 +1,13 @@
-TEST=*.py
-ARGS=
-
 PYTHON=python3
 #PYTHON=python
-#OPT=-m pdb
-#OPT=-m cProfile -s time
-#OPT=-m cProfile -o profile.rslt
 
 .PHONY: all
-all: test
+all: clean
 
 .PHONY: test
 test:
-	$(PYTHON) -m pytest -vv $(TEST)
+	$(PYTHON) -m pytest -vv
 
 .PHONY: clean
 clean:
-	rm -rf *.pyc __pycache__ parsetab.py *.out
+	rm -rf *.pyc __pycache__ parsetab.py *.out .cache
diff --git a/tests/dataflow_test/pyverilog b/tests/dataflow_test/pyverilog
diff --git a/tests/dataflow_test/test_dat_blocking.py b/tests/dataflow_test/test_dat_blocking.py
@@ -2,7 +2,7 @@
 import sys
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
 
-codedir = '../../testcode/'
+codedir = os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) + '/testcode/'
 
 expected = """\
 Directive:
diff --git a/tests/dataflow_test/test_dat_case.py b/tests/dataflow_test/test_dat_case.py
@@ -2,7 +2,7 @@
 import sys
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
 
-codedir = '../../testcode/'
+codedir = os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) + '/testcode/'
 
 expected = """\
 (Bind dest:TOP.cnt \
diff --git a/tests/dataflow_test/test_dat_case_in_func.py b/tests/dataflow_test/test_dat_case_in_func.py
@@ -1,12 +1,10 @@
 import os
 import sys
-sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) )
-
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
 from pyverilog.dataflow.optimizer import VerilogDataflowOptimizer
 from pyverilog.controlflow.controlflow_analyzer import VerilogControlflowAnalyzer
 
-codedir = '../../testcode/'
+codedir = os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) + '/testcode/'
 
 expected = """\
 TOP.IN1: TOP_IN1
diff --git a/tests/dataflow_test/test_dat_casex.py b/tests/dataflow_test/test_dat_casex.py
@@ -2,7 +2,7 @@
 import sys
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
 
-codedir = '../../testcode/'
+codedir = os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) + '/testcode/'
 
 expected = """\
 (Bind dest:TOP.cnt \
diff --git a/tests/dataflow_test/test_dat_decimal.py b/tests/dataflow_test/test_dat_decimal.py
@@ -2,7 +2,7 @@
 import sys
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
 
-codedir = '../../testcode/'
+codedir = os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) + '/testcode/'
 
 expected = """\
 (Bind dest:TOP.cnt \
diff --git a/tests/dataflow_test/test_dat_decimal_signed.py b/tests/dataflow_test/test_dat_decimal_signed.py
@@ -2,7 +2,7 @@
 import sys
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
 
-codedir = '../../testcode/'
+codedir = os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) + '/testcode/'
 
 expected = """\
 (Bind dest:TOP.cnt \
diff --git a/tests/dataflow_test/test_dat_decimal_width.py b/tests/dataflow_test/test_dat_decimal_width.py
@@ -2,7 +2,7 @@
 import sys
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
 
-codedir = '../../testcode/'
+codedir = os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) + '/testcode/'
 
 expected = """\
 (Bind dest:TOP.cnt \
diff --git a/tests/dataflow_test/test_dat_function.py b/tests/dataflow_test/test_dat_function.py
@@ -1,12 +1,10 @@
 import os
 import sys
-sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) )
-
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
 from pyverilog.dataflow.optimizer import VerilogDataflowOptimizer
 from pyverilog.controlflow.controlflow_analyzer import VerilogControlflowAnalyzer
 
-codedir = '../../testcode/'
+codedir = os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) + '/testcode/'
 
 expected = """\
 TOP.CLK: TOP_CLK
diff --git a/tests/dataflow_test/test_dat_generate.py b/tests/dataflow_test/test_dat_generate.py
@@ -2,7 +2,7 @@
 import sys
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
 
-codedir = '../../testcode/'
+codedir = os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) + '/testcode/'
 
 expected = """\
 (Bind dest:TOP.WD tree:(IntConst 4))
diff --git a/tests/dataflow_test/test_dat_generate_instance.py b/tests/dataflow_test/test_dat_generate_instance.py
@@ -2,7 +2,7 @@
 import sys
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
 
-codedir = '../../testcode/'
+codedir = os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) + '/testcode/'
 
 expected = """\
 (Bind dest:TOP.LEN tree:(IntConst 8))
diff --git a/tests/dataflow_test/test_dat_led.py b/tests/dataflow_test/test_dat_led.py
@@ -2,7 +2,7 @@
 import sys
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
 
-codedir = '../../testcode/'
+codedir = os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) + '/testcode/'
 
 expected = """\
 Directive:
diff --git a/tests/dataflow_test/test_dat_partial.py b/tests/dataflow_test/test_dat_partial.py
@@ -2,7 +2,7 @@
 import sys
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
 
-codedir = '../../testcode/'
+codedir = os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) + '/testcode/'
 
 expected = """\
 (Bind dest:TOP._rn0_i tree:(IntConst 0))
diff --git a/tests/dataflow_test/test_dat_partselect_assign.py b/tests/dataflow_test/test_dat_partselect_assign.py
@@ -1,12 +1,10 @@
 import os
 import sys
-sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) )
-
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
 from pyverilog.dataflow.optimizer import VerilogDataflowOptimizer
 from pyverilog.controlflow.controlflow_analyzer import VerilogControlflowAnalyzer
 
-codedir = '../../testcode/'
+codedir = os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) + '/testcode/'
 
 expected = """\
 TOP.CLK: TOP_CLK
diff --git a/tests/dataflow_test/test_dat_primitive.py b/tests/dataflow_test/test_dat_primitive.py
@@ -2,7 +2,7 @@
 import sys
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
 
-codedir = '../../testcode/'
+codedir = os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) + '/testcode/'
 
 expected = """\
 (Bind dest:TOP.out0 \
diff --git a/tests/dataflow_test/test_dat_ptr_clock_reset.py b/tests/dataflow_test/test_dat_ptr_clock_reset.py
@@ -2,7 +2,7 @@
 import sys
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
 
-codedir = '../../testcode/'
+codedir = os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) + '/testcode/'
 
 expected = """\
 (Bind dest:TOP.cnt \
diff --git a/tests/dataflow_test/test_dat_reset.py b/tests/dataflow_test/test_dat_reset.py
@@ -0,0 +1,30 @@
+import os
+import sys
+from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
+
+codedir = os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) + '/testcode/'
+
+expected = """\
+"""
+
+def test():
+    filelist = [codedir + 'reset.v']
+    topmodule = 'TOP'
+    noreorder = False
+    nobind = False
+    include = None
+    define = None
+
+    analyzer = VerilogDataflowAnalyzer(filelist, topmodule,
+                                       noreorder=noreorder,
+                                       nobind=nobind,
+                                       preprocess_include=include,
+                                       preprocess_define=define)
+    analyzer.generate()
+
+    #rslt = ''
+    #print(rslt)
+    #assert(expected == rslt)
+    
+if __name__ == '__main__':
+    test()
diff --git a/tests/dataflow_test/test_dat_signed_task.py b/tests/dataflow_test/test_dat_signed_task.py
@@ -2,7 +2,7 @@
 import sys
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
 
-codedir = '../../testcode/'
+codedir = os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) + '/testcode/'
 
 expected = """\
 (Bind dest:TOP.cnt \
diff --git a/tests/dataflow_test/test_dat_supply.py b/tests/dataflow_test/test_dat_supply.py
@@ -2,7 +2,7 @@
 import sys
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
 
-codedir = '../../testcode/'
+codedir = os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) + '/testcode/'
 
 expected = """\
 (Bind dest:TOP.AAA tree:(IntConst 1))
diff --git a/tests/dataflow_test/test_reset.py b/tests/dataflow_test/test_reset.py
diff --git a/tests/parser_test/Makefile b/tests/parser_test/Makefile
@@ -1,19 +1,13 @@
-TEST=*.py
-ARGS=
-
 PYTHON=python3
 #PYTHON=python
-#OPT=-m pdb
-#OPT=-m cProfile -s time
-#OPT=-m cProfile -o profile.rslt
 
 .PHONY: all
-all: test
+all: clean
 
 .PHONY: test
 test:
-	$(PYTHON) -m pytest -vv $(TEST)
+	$(PYTHON) -m pytest -vv
 
 .PHONY: clean
 clean:
-	rm -rf *.pyc __pycache__ parsetab.py *.out
+	rm -rf *.pyc __pycache__ parsetab.py *.out .cache
diff --git a/tests/parser_test/pyverilog b/tests/parser_test/pyverilog
diff --git a/tests/parser_test/test_par_delay.py b/tests/parser_test/test_par_delay.py
@@ -7,7 +7,7 @@
 except:
     from io import StringIO
 
-codedir = '../../testcode/'
+codedir = os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) + '/testcode/'
 
 expected = """\
 Source: 
diff --git a/tests/parser_test/test_par_escape.py b/tests/parser_test/test_par_escape.py
@@ -7,7 +7,7 @@
 except:
     from io import StringIO
 
-codedir = '../../testcode/'
+codedir = os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) + '/testcode/'
 
 expected = """\
 Source: 
diff --git a/tests/parser_test/test_par_instance_array.py b/tests/parser_test/test_par_instance_array.py
@@ -7,7 +7,7 @@
 except:
     from io import StringIO
 
-codedir = '../../testcode/'
+codedir = os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) + '/testcode/'
 
 expected = """\
 Source: 
diff --git a/tests/parser_test/test_par_led_main.py b/tests/parser_test/test_par_led_main.py
@@ -7,7 +7,7 @@
 except:
     from io import StringIO
 
-codedir = '../../testcode/'
+codedir = os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) + '/testcode/'
 
 expected = """\
 Source: 
diff --git a/tests/preprocessor_test/Makefile b/tests/preprocessor_test/Makefile
diff --git a/tests/preprocessor_test/pyverilog b/tests/preprocessor_test/pyverilog
diff --git a/tests/preprocessor_test/test_pre_led_main.py b/tests/preprocessor_test/test_pre_led_main.py
diff --git a/tests/pytest.ini b/tests/pytest.ini
