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Bug fixed for default_nettype and case statements with multiple match conditions.
1 parent 6a248df commit f60b41d

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7 files changed

+53
-10
lines changed

7 files changed

+53
-10
lines changed

dataflow/bindvisitor.py

Lines changed: 11 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@
99

1010
import sys
1111
import os
12+
import re
1213

1314
sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) )
1415

@@ -65,6 +66,10 @@ def getFrameTable(self):
6566
def start_visit(self):
6667
return self.visit(self.moduleinfotable.getDefinition(self.top))
6768

69+
def visit_ModuleDef(self, node):
70+
self.default_nettype = node.default_nettype
71+
self.generic_visit(node)
72+
6873
def visit_Input(self, node):
6974
self.addTerm(node)
7075

@@ -1215,12 +1220,12 @@ def getDst(self, left, scope):
12151220
if isinstance(left, Identifier):
12161221
name = self.searchTerminal(left.name, scope)
12171222
if name is None:
1218-
if self.default_nettype == 'none':
1219-
raise verror.FormatError()
1220-
if self.default_nettype == 'wire':
1221-
self.addTerm(Wire(left.name), rscope=scope)
1222-
if self.default_nettype == 'reg':
1223-
self.addTerm(Reg(left.name), rscope=scope)
1223+
m = re.search('none', self.default_nettype)
1224+
if m: raise verror.FormatError("No such signal: %s" % left.name)
1225+
m = re.search('wire', self.default_nettype)
1226+
if m: self.addTerm(Wire(left.name), rscope=scope)
1227+
m = re.search('reg', self.default_nettype)
1228+
if m: self.addTerm(Reg(left.name), rscope=scope)
12241229
name = self.searchTerminal(left.name, scope)
12251230
if left.scope is not None:
12261231
name = left.scope + ScopeLabel(left.name, 'signal')

dataflow/signalvisitor.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -215,7 +215,7 @@ def _case(self, comp, caselist):
215215
if len(case.cond) > 1:
216216
cond = Eq(comp, case.cond[0])
217217
for c in case.cond[1:]:
218-
cond = Lor(tmp, Eq(comp, c))
218+
cond = Lor(cond, Eq(comp, c))
219219
else:
220220
cond = Eq(comp, case.cond[0])
221221
label = self.labels.get( self.frames.getLabelKey('if') )

testcode/case.v

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,24 @@
1+
module TOP(CLK, RST, LED);
2+
input CLK, RST;
3+
output [7:0] LED;
4+
reg [7:0] cnt;
5+
always @(posedge CLK) begin
6+
if(RST) begin
7+
cnt <= 0;
8+
end else begin
9+
case(cnt)
10+
'h0, 'h1, 'h2: begin
11+
cnt <= cnt + 1;
12+
end
13+
'hff: begin
14+
cnt <= 0;
15+
end
16+
default: begin
17+
cnt <= cnt + 1;
18+
end
19+
endcase
20+
end
21+
end
22+
assign LED = cnt;
23+
endmodule
24+

testcode/test.v

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,10 @@
1+
//`default_nettype none
12

23
module TOP(CLK, RST, LED);
34
input CLK, RST;
45
output [7:0] LED;
56
reg [7:0] cnt;
7+
//wire enable;
68
localparam DELAYSIZE = 5;
79
always @(posedge CLK) begin
810
if(RST) begin
@@ -11,6 +13,7 @@ module TOP(CLK, RST, LED);
1113
cnt <= #DELAYSIZE cnt==255? 0 : cnt + 1;
1214
end
1315
end
14-
assign LED = cnt;
16+
assign enable = cnt == 'hff;
17+
assign LED = enable? 'hff : 0;
1518
endmodule
1619

vparser/ast.py

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -68,11 +68,12 @@ def children(self):
6868

6969
class ModuleDef(Node):
7070
attr_names = ('name',)
71-
def __init__(self, name, paramlist, portlist, items):
71+
def __init__(self, name, paramlist, portlist, items, default_nettype='wire'):
7272
self.name = name
7373
self.paramlist = paramlist
7474
self.portlist = portlist
7575
self.items = items
76+
self.default_nettype = default_nettype
7677
def children(self):
7778
nodelist = []
7879
if self.paramlist is not None: nodelist.append(self.paramlist)

vparser/lexer.py

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,7 @@ def __init__(self, error_func):
2222
self.filename = ''
2323
self.error_func = error_func
2424
self.directives = []
25+
self.default_nettype = 'wire'
2526

2627
def build(self, **kwargs):
2728
self.lexer = ply.lex.lex(object=self, **kwargs)
@@ -34,6 +35,9 @@ def reset_lineno(self):
3435
def get_directives(self):
3536
return tuple(self.directives)
3637

38+
def get_default_nettype(self):
39+
return self.default_nettype
40+
3741
def token(self):
3842
return self.lexer.token()
3943

@@ -91,6 +95,8 @@ def token(self):
9195
def t_DIRECTIVE(self, t):
9296
self.directives.append( (self.lexer.lineno, t.value) )
9397
t.lexer.lineno += t.value.count("\n")
98+
m = re.match("^`default_nettype\s+(.+)\n", t.value)
99+
if m: self.default_nettype = m.group(1)
94100
pass
95101

96102
# Comment

vparser/parser.py

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -57,6 +57,9 @@ def _lexer_error_func(self, msg, line, column):
5757

5858
def get_directives(self):
5959
return self.lexer.get_directives()
60+
61+
def get_default_nettype(self):
62+
return self.lexer.get_default_nettype()
6063

6164
# Returns AST
6265
def parse(self, text, debug=0):
@@ -101,7 +104,8 @@ def p_pragma(self, p):
101104
######################################################################
102105
def p_moduledef(self,p):
103106
'moduledef : MODULE modulename paramlist portlist items ENDMODULE'
104-
p[0] = ModuleDef(name=p[2], paramlist=p[3], portlist=p[4], items=p[5])
107+
p[0] = ModuleDef(name=p[2], paramlist=p[3], portlist=p[4], items=p[5],
108+
default_nettype=self.get_default_nettype())
105109

106110
def p_modulename(self, p):
107111
'modulename : ID'

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