Merge branch 'leonardt-master' into develop

Author: shtaxxx

pyverilog/vparser/ast.py

@@ -14,10 +14,10 @@
 
 class Node(object):
     '''Abstact class for every element in parser'''
-    
+
     def children(self):
         pass
-    
+
     def show(self, buf=sys.stdout, offset=0, attrnames=False, showlineno=True):
         indent = 2
         lead = ' ' * offset
@@ -35,7 +35,7 @@ def show(self, buf=sys.stdout, offset=0, attrnames=False, showlineno=True):
         buf.write('\n')
         for c in self.children():
             c.show(buf, offset + indent, attrnames, showlineno)
-            
+
     def __eq__(self, other):
         if type(self) != type(other): return False
         self_attrs = tuple( [ getattr(self, a) for a in self.attr_names ] )
@@ -45,10 +45,10 @@ def __eq__(self, other):
         for i, c in enumerate(self.children()):
             if c != other_children[i]: return False
         return True
-    
+
     def __ne__(self, other):
         return not self.__eq__(other)
-    
+
     def __hash__(self):
         s = hash(tuple([getattr(self, a) for a in self.attr_names]))
         c = hash(self.children())
@@ -458,6 +458,12 @@ def children(self):
         if self.statement: nodelist.append(self.statement)
         return tuple(nodelist)
 
+class AlwaysFF(Always):
+    pass
+
+class AlwaysComb(Always):
+    pass
+
 class SensList(Node):
     attr_names = ()
     def __init__(self, list, lineno=0):
@@ -553,6 +559,8 @@ def children(self):
 
 class CasexStatement(CaseStatement): pass
 
+class UniqueCaseStatement(CaseStatement): pass
+
 class Case(Node):
     attr_names = ()
     def __init__(self, cond, statement, lineno=0):

pyverilog/vparser/lexer.py

@@ -43,10 +43,10 @@ def token(self):
     keywords = (
         'MODULE', 'ENDMODULE', 'BEGIN', 'END', 'GENERATE', 'ENDGENERATE', 'GENVAR',
         'FUNCTION', 'ENDFUNCTION', 'TASK', 'ENDTASK',
-        'INPUT', 'INOUT', 'OUTPUT', 'TRI', 'REG', 'WIRE', 'INTEGER', 'REAL', 'SIGNED',
+        'INPUT', 'INOUT', 'OUTPUT', 'TRI', 'REG', 'LOGIC', 'WIRE', 'INTEGER', 'REAL', 'SIGNED',
         'PARAMETER', 'LOCALPARAM', 'SUPPLY0', 'SUPPLY1',
-        'ASSIGN', 'ALWAYS', 'SENS_OR', 'POSEDGE', 'NEGEDGE', 'INITIAL',
-        'IF', 'ELSE', 'FOR', 'WHILE', 'CASE', 'CASEX', 'ENDCASE', 'DEFAULT',
+        'ASSIGN', 'ALWAYS', 'ALWAYS_FF', 'ALWAYS_COMB', 'SENS_OR', 'POSEDGE', 'NEGEDGE', 'INITIAL',
+        'IF', 'ELSE', 'FOR', 'WHILE', 'CASE', 'CASEX', 'UNIQUE', 'ENDCASE', 'DEFAULT',
         'WAIT', 'FOREVER', 'DISABLE', 'FORK', 'JOIN',
         )
 
@@ -266,18 +266,18 @@ def dump_tokens(text):
     def my_error_func(msg, a, b):
         sys.write(msg + "\n")
         sys.exit()
-        
+
     lexer = VerilogLexer(error_func=my_error_func)
     lexer.build()
     lexer.input(text)
 
     ret = []
-    
+
     # Tokenize
     while True:
         tok = lexer.token()
         if not tok: break # No more input
         ret.append("%s %s %d %s %d\n" %
                    (tok.value, tok.type, tok.lineno, lexer.filename, tok.lexpos))
-        
+
     return ''.join(ret)

pyverilog/vparser/parser.py

@@ -115,6 +115,7 @@ def p_moduledef(self, p):
         p[0] = ModuleDef(name=p[2], paramlist=p[3], portlist=p[4], items=p[5],
                          default_nettype=self.get_default_nettype(), lineno=p.lineno(1))
         p.set_lineno(0, p.lineno(1))
+        p[0].end_lineno = p.lineno(6)
 
     def p_modulename(self, p):
         'modulename : ID'
@@ -299,6 +300,11 @@ def p_sigtype_reg(self, p):
         p[0] = p[1]
         p.set_lineno(0, p.lineno(1))
 
+    def p_sigtype_logic(self, p):
+        'sigtype : LOGIC'
+        p[0] = p[1]
+        p.set_lineno(0, p.lineno(1))
+
     def p_sigtype_wire(self, p):
         'sigtype : WIRE'
         p[0] = p[1]
@@ -458,6 +464,8 @@ def p_standard_item(self, p):
         | genvardecl
         | assignment
         | always
+        | always_ff
+        | always_comb
         | initial
         | instance
         | function
@@ -1255,6 +1263,14 @@ def p_always(self, p):
         p[0] = Always(p[2], p[3], lineno=p.lineno(1))
         p.set_lineno(0, p.lineno(1))
 
+    def p_always_ff(self, p):
+        'always_ff : ALWAYS_FF senslist always_statement'
+        p[0] = AlwaysFF(p[2], p[3], lineno=p.lineno(1))
+
+    def p_always_comb(self, p):
+        'always_comb : ALWAYS_COMB senslist always_statement'
+        p[0] = AlwaysComb(p[2], p[3], lineno=p.lineno(1))
+
     def p_sens_egde_paren(self, p):
         'senslist : AT LPAREN edgesigs RPAREN'
         p[0] = SensList(p[3], lineno=p.lineno(1))
@@ -1357,6 +1373,7 @@ def p_basic_statement(self, p):
         """basic_statement : if_statement
         | case_statement
         | casex_statement
+        | unique_case_statement
         | for_statement
         | while_statement
         | event_statement
@@ -1599,6 +1616,12 @@ def p_casex_statement(self, p):
         p[0] = CasexStatement(p[3], p[5], lineno=p.lineno(1))
         p.set_lineno(0, p.lineno(1))
 
+    def p_unique_case_statement(self, p):
+        'unique_case_statement : UNIQUE CASE LPAREN case_comp RPAREN casecontent_statements ENDCASE'
+        p[0] = UniqueCaseStatement(p[3], p[5], lineno=p.lineno(1))
+        p.set_lineno(0, p.lineno(1))
+
+
     def p_case_comp(self, p):
         'case_comp : expression'
         p[0] = p[1]