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Merge branch 'work2'
2 parents c6f3858 + bdb4d73 commit e45d75b

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4 files changed

+27
-4
lines changed

4 files changed

+27
-4
lines changed

pyverilog/dataflow/bindvisitor.py

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1095,9 +1095,9 @@ def makeDFTree(self, node, scope):
10951095

10961096
if isinstance(node, SystemCall):
10971097
if node.syscall == 'unsigned':
1098-
return self.makeDFTree(node.args[0])
1098+
return self.makeDFTree(node.args[0], scope)
10991099
if node.syscall == 'signed':
1100-
return self.makeDFTree(node.args[0])
1100+
return self.makeDFTree(node.args[0], scope)
11011101
return DFIntConst('0')
11021102

11031103
raise verror.FormatError("unsupported AST node type: %s %s" %

pyverilog/testcode/signed_task.v

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,14 @@
1+
module TOP(CLK, RST);
2+
input CLK, RST;
3+
reg [7:0] cnt;
4+
5+
always @(posedge CLK or negedge RST) begin
6+
if(RST) begin
7+
cnt <= $signed(cnt);
8+
end else begin
9+
cnt <= $unsigned(cnt);
10+
end
11+
end
12+
13+
14+
endmodule

pyverilog/testcode/test_sd.py

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
#-------------------------------------------------------------------------------
22
# test_sd.py
33
#
4-
# Lexical analyzer
4+
#
55
#
66
# Copyright (C) 2015, ryosuke fukatani
77
# License: Apache 2.0
@@ -32,6 +32,11 @@ def test_signed(self):
3232
self.assertEqual(binddict.values()[0][0].tostr(),
3333
"(Bind dest:TOP.cnt tree:(Branch Cond:(Terminal TOP.RST) True:(IntConst 'd0) False:(Operator Plus Next:(Terminal TOP.cnt),(IntConst 1'sd1))))")
3434

35+
def test_signed_task(self):
36+
terms, binddict = self.dataflow_wrapper("signed_task.v")
37+
self.assertEqual(binddict.values()[0][0].tostr(),
38+
"(Bind dest:TOP.cnt tree:(Branch Cond:(Terminal TOP.RST) True:(Terminal TOP.cnt) False:(Terminal TOP.cnt)))")
39+
3540
def test_casex(self):
3641
self.dataflow_wrapper("casex.v")
3742

pyverilog/vparser/parser.py

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
# Parser
55
#
66
# Copyright (C) 2013, Shinya Takamaeda-Yamazaki
7-
# edited by ryosuke fukatani
7+
# modified by ryosuke fukatani
88
# License: Apache 2.0
99
#-------------------------------------------------------------------------------
1010

@@ -1550,6 +1550,10 @@ def p_systemcall(self, p):
15501550
'systemcall : DOLLER ID LPAREN sysargs RPAREN'
15511551
p[0] = SystemCall(p[2], p[4])
15521552

1553+
def p_systemcall_signed(self, p):#for $signed system task
1554+
'systemcall : DOLLER SIGNED LPAREN sysargs RPAREN'
1555+
p[0] = SystemCall(p[2], p[4])
1556+
15531557
def p_sysargs(self, p):
15541558
'sysargs : sysargs COMMA sysarg'
15551559
p[0] = p[1] + (p[3],)

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