Merge pull request #51 from leonardt/add-nd-arrays

shtaxxx · web-flow · commit dd331d35c17d · 2019-11-16T21:05:12.000+09:00
Extend parser for n-d array support
diff --git a/pyverilog/ast_code_generator/codegen.py b/pyverilog/ast_code_generator/codegen.py
@@ -258,6 +258,7 @@ def visit_Variable(self, node):
             'name': escape(node.name),
             'width': '' if node.width is None else self.visit(node.width),
             'signed': node.signed,
+            'dimensions': '' if node.dimensions is None else self.visit(node.dimensions),
         }
         rslt = template.render(template_dict)
         return rslt
@@ -269,6 +270,7 @@ def visit_Input(self, node):
             'name': escape(node.name),
             'width': '' if node.width is None else self.visit(node.width),
             'signed': node.signed,
+            'dimensions': '' if node.dimensions is None else self.visit(node.dimensions),
         }
         rslt = template.render(template_dict)
         return rslt
@@ -280,6 +282,7 @@ def visit_Output(self, node):
             'name': escape(node.name),
             'width': '' if node.width is None else self.visit(node.width),
             'signed': node.signed,
+            'dimensions': '' if node.dimensions is None else self.visit(node.dimensions),
         }
         rslt = template.render(template_dict)
         return rslt
@@ -291,6 +294,7 @@ def visit_Inout(self, node):
             'name': escape(node.name),
             'width': '' if node.width is None else self.visit(node.width),
             'signed': node.signed,
+            'dimensions': '' if node.dimensions is None else self.visit(node.dimensions),
         }
         rslt = template.render(template_dict)
         return rslt
@@ -302,6 +306,7 @@ def visit_Tri(self, node):
             'name': escape(node.name),
             'width': '' if node.width is None else self.visit(node.width),
             'signed': node.signed,
+            'dimensions': '' if node.dimensions is None else self.visit(node.dimensions),
         }
         rslt = template.render(template_dict)
         return rslt
@@ -313,6 +318,7 @@ def visit_Wire(self, node):
             'name': escape(node.name),
             'width': '' if node.width is None else self.visit(node.width),
             'signed': node.signed,
+            'dimensions': '' if node.dimensions is None else self.visit(node.dimensions),
         }
         rslt = template.render(template_dict)
         return rslt
@@ -324,30 +330,7 @@ def visit_Reg(self, node):
             'name': escape(node.name),
             'width': '' if node.width is None else self.visit(node.width),
             'signed': node.signed,
-        }
-        rslt = template.render(template_dict)
-        return rslt
-
-    def visit_WireArray(self, node):
-        filename = getfilename(node)
-        template = self.get_template(filename)
-        template_dict = {
-            'name': escape(node.name),
-            'width': '' if node.width is None else self.visit(node.width),
-            'length': self.visit(node.length),
-            'signed': node.signed,
-        }
-        rslt = template.render(template_dict)
-        return rslt
-
-    def visit_RegArray(self, node):
-        filename = getfilename(node)
-        template = self.get_template(filename)
-        template_dict = {
-            'name': escape(node.name),
-            'width': '' if node.width is None else self.visit(node.width),
-            'length': self.visit(node.length),
-            'signed': node.signed,
+            'dimensions': '' if node.dimensions is None else self.visit(node.dimensions),
         }
         rslt = template.render(template_dict)
         return rslt
@@ -388,7 +371,8 @@ def visit_Ioport(self, node):
             'second': '' if node.second is None else node.second.__class__.__name__.lower(),
             'name': escape(node.first.name),
             'width': '' if node.first.width is None else self.visit(node.first.width),
-            'signed': node.first.signed or (node.second is not None and node.second.signed)
+            'signed': node.first.signed or (node.second is not None and node.second.signed),
+            'dimensions': '' if node.first.dimensions is None else self.visit(node.first.dimensions)
         }
         rslt = template.render(template_dict)
         return rslt
diff --git a/pyverilog/ast_code_generator/list_ast.txt b/pyverilog/ast_code_generator/list_ast.txt
@@ -6,6 +6,7 @@ Portlist
 Port
 Width
 Length
+Dimensions
 Identifier
 Value
 Constant
@@ -19,8 +20,6 @@ Inout
 Tri
 Wire
 Reg
-WireArray
-RegArray
 Integer
 Real
 Genvar
diff --git a/pyverilog/ast_code_generator/template/inout.txt b/pyverilog/ast_code_generator/template/inout.txt
@@ -1 +1 @@
-inout {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }};
+inout {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }}{% if dimensions != '' %} {{ dimensions }}{% endif %};
diff --git a/pyverilog/ast_code_generator/template/input.txt b/pyverilog/ast_code_generator/template/input.txt
@@ -1 +1 @@
-input {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }};
+input {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }}{% if dimensions != '' %} {{ dimensions }}{% endif %};
diff --git a/pyverilog/ast_code_generator/template/ioport.txt b/pyverilog/ast_code_generator/template/ioport.txt
@@ -1 +1 @@
-{{ first }} {% if second != '' %}{{ second }} {% endif %}{% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }}
+{{ first }} {% if second != '' %}{{ second }} {% endif %}{% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }}{% if dimensions != '' %} {{ dimensions }}{% endif %}
diff --git a/pyverilog/ast_code_generator/template/output.txt b/pyverilog/ast_code_generator/template/output.txt
@@ -1 +1 @@
-output {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }};
+output {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }}{% if dimensions != '' %} {{ dimensions }}{% endif %};
diff --git a/pyverilog/ast_code_generator/template/reg.txt b/pyverilog/ast_code_generator/template/reg.txt
@@ -1 +1 @@
-reg {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }};
+reg {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }}{% if dimensions != '' %} {{ dimensions }}{% endif %};
diff --git a/pyverilog/ast_code_generator/template/regarray.txt b/pyverilog/ast_code_generator/template/regarray.txt
diff --git a/pyverilog/ast_code_generator/template/tri.txt b/pyverilog/ast_code_generator/template/tri.txt
@@ -1 +1 @@
-tri {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }};
+tri {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }}{% if dimensions != '' %} {{ dimensions }}{% endif %};
diff --git a/pyverilog/ast_code_generator/template/variable.txt b/pyverilog/ast_code_generator/template/variable.txt
@@ -1 +1 @@
-variable {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }};
+variable {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }}{% if dimensions != '' %} {{ dimensions }}{% endif %};
diff --git a/pyverilog/ast_code_generator/template/wire.txt b/pyverilog/ast_code_generator/template/wire.txt
@@ -1 +1 @@
-wire {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }};
+wire {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }}{% if dimensions != '' %} {{ dimensions }}{% endif %};
diff --git a/pyverilog/ast_code_generator/template/wirearray.txt b/pyverilog/ast_code_generator/template/wirearray.txt
diff --git a/pyverilog/dataflow/bindvisitor.py b/pyverilog/dataflow/bindvisitor.py
@@ -828,9 +828,6 @@ def addTerm(self, node, rscope=None):
 
         lenmsb = None
         lenlsb = None
-        if isinstance(node, RegArray) or isinstance(node, WireArray):
-            lenmsb = self.makeDFTree(node.length.msb, scope)
-            lenlsb = self.makeDFTree(node.length.lsb, scope)
 
         term = Term(name, termtypes, msb, lsb, lenmsb, lenlsb)
         self.dataflow.addTerm(name, term)
diff --git a/pyverilog/vparser/ast.py b/pyverilog/vparser/ast.py
@@ -183,6 +183,20 @@ class Length(Width):
     pass
 
 
+class Dimensions(Node):
+    attr_names = ()
+
+    def __init__(self, lengths, lineno=0):
+        self.lineno = lineno
+        self.lengths = lengths
+
+    def children(self):
+        nodelist = []
+        if self.lengths:
+            nodelist = self.lengths
+        return tuple(nodelist)
+
+
 class Identifier(Node):
     attr_names = ('name',)
 
@@ -247,16 +261,19 @@ class StringConst(Constant):
 class Variable(Value):
     attr_names = ('name', 'signed')
 
-    def __init__(self, name, width=None, signed=False, lineno=0):
+    def __init__(self, name, width=None, signed=False, dimensions=None, lineno=0):
         self.lineno = lineno
         self.name = name
         self.width = width
         self.signed = signed
+        self.dimensions = dimensions
 
     def children(self):
         nodelist = []
         if self.width:
             nodelist.append(self.width)
+        if self.dimensions:
+            nodelist.append(self.dimensions)
         return tuple(nodelist)
 
 
@@ -284,44 +301,6 @@ class Reg(Variable):
     pass
 
 
-class WireArray(Variable):
-    attr_names = ('name', 'signed')
-
-    def __init__(self, name, width, length, signed=False, lineno=0):
-        self.lineno = lineno
-        self.name = name
-        self.width = width
-        self.length = length
-        self.signed = signed
-
-    def children(self):
-        nodelist = []
-        if self.width:
-            nodelist.append(self.width)
-        if self.length:
-            nodelist.append(self.length)
-        return tuple(nodelist)
-
-
-class RegArray(Variable):
-    attr_names = ('name', 'signed')
-
-    def __init__(self, name, width, length, signed=False, lineno=0):
-        self.lineno = lineno
-        self.name = name
-        self.width = width
-        self.length = length
-        self.signed = signed
-
-    def children(self):
-        nodelist = []
-        if self.width:
-            nodelist.append(self.width)
-        if self.length:
-            nodelist.append(self.length)
-        return tuple(nodelist)
-
-
 class Integer(Variable):
     pass
 
diff --git a/pyverilog/vparser/parser.py b/pyverilog/vparser/parser.py

Original file line number	Diff line number	Diff line change
`@@ -1 +1 @@`
`1`		`-inout {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }};`
	`1`	`+inout {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }}{% if dimensions != '' %} {{ dimensions }}{% endif %};`
Original file line number	Diff line number	Diff line change
`@@ -1 +1 @@`
`1`		`-input {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }};`
	`1`	`+input {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }}{% if dimensions != '' %} {{ dimensions }}{% endif %};`
Original file line number	Diff line number	Diff line change
`@@ -1 +1 @@`
`1`		`-{{ first }} {% if second != '' %}{{ second }} {% endif %}{% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }}`
	`1`	`+{{ first }} {% if second != '' %}{{ second }} {% endif %}{% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }}{% if dimensions != '' %} {{ dimensions }}{% endif %}`
Original file line number	Diff line number	Diff line change
`@@ -1 +1 @@`
`1`		`-output {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }};`
	`1`	`+output {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }}{% if dimensions != '' %} {{ dimensions }}{% endif %};`
Original file line number	Diff line number	Diff line change
`@@ -1 +1 @@`
`1`		`-reg {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }};`
	`1`	`+reg {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }}{% if dimensions != '' %} {{ dimensions }}{% endif %};`
Original file line number	Diff line number	Diff line change
`@@ -1 +1 @@`
`1`		`-tri {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }};`
	`1`	`+tri {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }}{% if dimensions != '' %} {{ dimensions }}{% endif %};`
Original file line number	Diff line number	Diff line change
`@@ -1 +1 @@`
`1`		`-variable {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }};`
	`1`	`+variable {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }}{% if dimensions != '' %} {{ dimensions }}{% endif %};`