A pytest module for ast_code_generator is added. Jinja2 template of moduledef is updated.

Author: shtaxxx

pyverilog/ast_code_generator/codegen.py

@@ -984,6 +984,8 @@ def showVersion():
                          default=False,help="Show the version")
     optparser.add_option("-I","--include",dest="include",action="append",
                          default=[],help="Include path")
+    optparser.add_option("-D",dest="define",action="append",
+                         default=[],help="Macro Definition")
     (options, args) = optparser.parse_args()
 
     filelist = args
@@ -996,7 +998,10 @@ def showVersion():
     if len(filelist) == 0:
         showVersion()
 
-    codeparser = VerilogCodeParser(filelist, preprocess_include=options.include)
+    codeparser = VerilogCodeParser(filelist,
+                                   preprocess_include=options.include,
+                                   preprocess_define=options.define)
+
     ast = codeparser.parse()
     directives = codeparser.get_directives()
 

pyverilog/ast_code_generator/template/moduledef.txt

@@ -11,3 +11,4 @@ module {{ modulename }}{% if paramlist != '' %} #
 {% for item in items %}{{ item }}
 {% endfor %}
 endmodule
+

tests/ast_code_generator_test/Makefile

@@ -0,0 +1,19 @@
+TEST=*.py
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv $(TEST)
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py *.out

tests/ast_code_generator_test/pyverilog

@@ -0,0 +1 @@
+../../pyverilog/

tests/ast_code_generator_test/test_assign.py

@@ -0,0 +1,37 @@
+import os
+import sys
+import pyverilog.vparser.ast as vast
+from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
+
+expected = """\
+
+module top
+(
+  input CLK,
+  input RST,
+  output [7:0] led
+);
+
+  assign led = 8;
+
+endmodule
+"""
+
+def test():
+    params = vast.Paramlist(())
+    clk = vast.Ioport( vast.Input('CLK') )
+    rst = vast.Ioport( vast.Input('RST') )
+    width = vast.Width( vast.IntConst('7'), vast.IntConst('0') )
+    led = vast.Ioport( vast.Output('led', width=width) )
+    ports = vast.Portlist( (clk, rst, led) )
+    items = ( vast.Assign( vast.Identifier('led'), vast.IntConst('8') ) ,)
+    ast = vast.ModuleDef("top", params, ports, items)
+    
+    codegen = ASTCodeGenerator()
+    rslt = codegen.visit(ast)
+    
+    print(rslt)
+    assert(rslt == expected)
+
+if __name__ == '__main__':
+    test()