Makefiles are updated for the location modification of testcode

Author: shtaxxx

pyverilog/ast_code_generator/Makefile

@@ -4,7 +4,7 @@ PYTHON=python3
 #OPT=-m cProfile -o profile.rslt
 
 CODEGEN=codegen.py
-SRCS=../testcode/test.v
+SRCS=../../testcode/led.v
 
 .PHONY: codegen
 codegen:

pyverilog/controlflow/Makefile

@@ -8,7 +8,7 @@ ANALYZER=controlflow_analyzer.py
 ACTIVE=active_analyzer.py
 ACTIVERANGE=active_range.py
 
-SRCS=../testcode/vectoradd.v
+SRCS=../../testcode/vectoradd.v
 TOP=-t TOP
 TARGETS=-s "TOP.MEM_A"
 

pyverilog/dataflow/Makefile

@@ -12,7 +12,7 @@ SUBSET=subset.py
 CODEGEN=codegen.py
 GRAPHGEN=graphgen.py
 
-SRCS=../testcode/generate.v
+SRCS=../../testcode/generate.v
 TOP=-t TOP
 TARGETS=-s "TOP.OUT4"
 

setup.py

@@ -1,4 +1,4 @@
-from setuptools import setup, find_packages
+ppfrom setuptools import setup, find_packages
 
 import pyverilog.utils.version
 import re
@@ -20,7 +20,5 @@ def read(filename):
       license="Apache License 2.0",
       url='http://shtaxxx.github.io/Pyverilog/',
       packages=find_packages(),
-      package_data={ 'pyverilog.ast_code_generator' : ['template/*'], 
-                     'pyverilog' : ['testcode/*'], },
+      package_data={ 'pyverilog.ast_code_generator' : ['template/*'],  },
 )
-