4'sdのようなコードを解釈できないため修整。lexer内のtoken解釈をする順番を入れ替えただけ。

casex文についてcase文と同様に解釈する機能の追加

上記確認テストの追加。

Author: fukatani

pyverilog/testcode/casex.v

@@ -0,0 +1,24 @@
+module TOP(CLK, RST, LED);
+  input CLK, RST;
+  output [7:0] LED;
+  reg [7:0] cnt;
+  always @(posedge CLK) begin
+    if(RST) begin
+      cnt <= 0;
+    end else begin
+      casex(cnt)
+        'b00: begin
+          cnt <= cnt + 1;
+        end
+        'b1x: begin
+          cnt <= 0;
+        end
+        default: begin
+          cnt <= cnt + 1;
+        end
+      endcase
+    end
+  end
+  assign LED = cnt;
+endmodule
+

pyverilog/testcode/signed.v

@@ -0,0 +1,18 @@
+//`default_nettype none
+
+module TOP(CLK, RST);
+  input CLK, RST;
+  reg [7:0] cnt;
+
+
+  always @(posedge CLK or negedge RST) begin
+    if(RST) begin
+      cnt <= 'd0;
+    end else begin
+      cnt <= cnt + 1'sd1;
+    end
+  end
+
+
+endmodule
+

pyverilog/testcode/test_sd.py

@@ -0,0 +1,108 @@
+#-------------------------------------------------------------------------------
+# test_sd.py
+#
+# Lexical analyzer
+#
+# Copyright (C) 2015, ryosuke fukatani
+# License: Apache 2.0
+#-------------------------------------------------------------------------------
+
+
+import sys
+import os
+import subprocess
+
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) )
+
+from pyverilog.dataflow.dataflow_analyzer import *
+import unittest
+
+
+class TestSequenceFunctions(unittest.TestCase):
+    def setUp(self):
+        path_clone = sys.path
+        pop_target = []
+        for i,path in enumerate(path_clone):
+            if path == 'C:\\Python27\\lib\\site-packages\\pyverilog-0.9.0-py2.7.egg':
+                pop_target.append(i)
+        for i in reversed(pop_target):
+            sys.path.pop(i)
+        reload(pyverilog.dataflow.dataflow_analyzer)
+
+    def test_signed(self):
+        terms, binddict = self.dataflow_wrapper("signed.v")
+        self.assertEqual(binddict.values()[0][0].tostr(),
+        "(Bind dest:TOP.cnt tree:(Branch Cond:(Terminal TOP.RST) True:(IntConst 'd0) False:(Operator Plus Next:(Terminal TOP.cnt),(IntConst 1'sd1))))")
+
+    def test_casex(self):
+        self.dataflow_wrapper("casex.v")
+
+    def dataflow_wrapper(self,code_file):
+
+        from optparse import OptionParser
+
+        optparser = OptionParser()
+        optparser.add_option("-v","--version",action="store_true",dest="showversion",
+                             default=False,help="Show the version")
+        optparser.add_option("-I","--include",dest="include",action="append",
+                             default=[],help="Include path")
+        optparser.add_option("-D",dest="define",action="append",
+                             default=[],help="Macro Definition")
+        optparser.add_option("-t","--top",dest="topmodule",
+                             default="TOP",help="Top module, Default=TOP")
+        optparser.add_option("--nobind",action="store_true",dest="nobind",
+                             default=False,help="No binding traversal, Default=False")
+        optparser.add_option("--noreorder",action="store_true",dest="noreorder",
+                             default=False,help="No reordering of binding dataflow, Default=False")
+
+        filelist = {code_file}
+        options = optparser.get_default_values()
+
+
+        for f in filelist:
+            if not os.path.exists(f): raise IOError("file not found: " + f)
+
+        verilogdataflowanalyzer = VerilogDataflowAnalyzer(filelist, options.topmodule,
+                                                          noreorder=options.noreorder,
+                                                          nobind=options.nobind,
+                                                          preprocess_include=options.include,
+                                                          preprocess_define=options.define)
+        verilogdataflowanalyzer.generate()
+
+        directives = verilogdataflowanalyzer.get_directives()
+        print('Directive:')
+        for dr in directives:
+            print(dr)
+
+        instances = verilogdataflowanalyzer.getInstances()
+        print('Instance:')
+        for ins in instances:
+            print(ins)
+
+        if options.nobind:
+            print('Signal:')
+            signals = verilogdataflowanalyzer.getSignals()
+            for sig in signals:
+                print(sig)
+
+            print('Const:')
+            consts = verilogdataflowanalyzer.getConsts()
+            for con in consts:
+                print(con)
+
+        else:
+            terms = verilogdataflowanalyzer.getTerms()
+            print('Term:')
+            for tk, tv in sorted(terms.items(), key=lambda x:len(x[0])):
+                print(tv.tostr())
+
+            binddict = verilogdataflowanalyzer.getBinddict()
+            print('Bind:')
+            for bk, bv in sorted(binddict.items(), key=lambda x:len(x[0])):
+                for bvi in bv:
+                    print(bvi.tostr())
+
+        return terms, binddict
+
+if __name__ == '__main__':
+    unittest.main()

pyverilog/vparser/ast.py

@@ -1,9 +1,10 @@
 #-------------------------------------------------------------------------------
 # ast.py
-# 
+#
 # Verilog HDL AST classes with Pyverilog
 #
 # Copyright (C) 2013, Shinya Takamaeda-Yamazaki
+# edited by ryosuke fukatani
 # License: Apache 2.0
 #-------------------------------------------------------------------------------
 
@@ -47,7 +48,7 @@ def __hash__(self):
         s = hash(tuple([getattr(self, a) for a in self.attr_names]))
         c = hash(self.children())
         return hash((s, c))
-        
+
 ################################################################################
 class Source(Node):
     attr_names = ('name',)
@@ -171,7 +172,7 @@ def children(self):
         nodelist = []
         if self.width: nodelist.append(self.width)
         return tuple(nodelist)
-        
+
 class Input(Variable): pass
 class Output(Variable): pass
 class Inout(Variable): pass
@@ -347,11 +348,11 @@ class Power(Operator): pass
 class Times(Operator): pass
 class Divide(Operator): pass
 class Mod(Operator): pass
-################################################################################    
+################################################################################
 # Level 3
 class Plus(Operator): pass
 class Minus(Operator): pass
-################################################################################    
+################################################################################
 # Level 4
 class Sll(Operator): pass
 class Srl(Operator): pass
@@ -510,6 +511,8 @@ def children(self):
         if self.caselist: nodelist.extend(self.caselist)
         return tuple(nodelist)
 
+class CasexStatement(CaseStatement): pass
+
 class Case(Node):
     attr_names = ()
     def __init__(self, cond, statement):
@@ -540,7 +543,7 @@ def children(self):
         if self.statement: nodelist.append(self.statement)
         return tuple(nodelist)
 
-class EventStatement(Node): 
+class EventStatement(Node):
     attr_names = ()
     def __init__(self, senslist):
         self.senslist = senslist
@@ -589,7 +592,7 @@ def children(self):
         if self.parameterlist: nodelist.extend(self.parameterlist)
         if self.instances: nodelist.extend(self.instances)
         return tuple(nodelist)
-    
+
 class Instance(Node):
     attr_names = ('name', 'module')
     def __init__(self, module, name, portlist, parameterlist, array=None):

pyverilog/vparser/lexer.py

@@ -1,9 +1,12 @@
 #-------------------------------------------------------------------------------
 # lexer.py
-# 
+#
 # Lexical analyzer
 #
 # Copyright (C) 2013, Shinya Takamaeda-Yamazaki
+#
+# edited by ryosuke fukatani
+#
 # License: Apache 2.0
 #-------------------------------------------------------------------------------
 
@@ -45,9 +48,9 @@ def token(self):
         'MODULE', 'ENDMODULE', 'BEGIN', 'END', 'GENERATE', 'ENDGENERATE', 'GENVAR',
         'FUNCTION', 'ENDFUNCTION', 'TASK', 'ENDTASK',
         'INPUT', 'INOUT', 'OUTPUT', 'TRI', 'REG', 'WIRE', 'INTEGER', 'REAL', 'SIGNED',
-        'PARAMETER', 'LOCALPARAM', 
+        'PARAMETER', 'LOCALPARAM',
         'ASSIGN', 'ALWAYS', 'SENS_OR', 'POSEDGE', 'NEGEDGE', 'INITIAL',
-        'IF', 'ELSE', 'FOR', 'WHILE', 'CASE', 'ENDCASE', 'DEFAULT',
+        'IF', 'ELSE', 'FOR', 'WHILE', 'CASE', 'CASEX', 'ENDCASE', 'DEFAULT',
         'WAIT', 'FOREVER', 'DISABLE', 'FORK', 'JOIN',
         )
 
@@ -62,7 +65,7 @@ def token(self):
         'PLUS','MINUS','POWER','TIMES','DIVIDE','MOD',
         'NOT', 'OR', 'NOR', 'AND', 'NAND', 'XOR', 'XNOR',
         'LOR', 'LAND', 'LNOT',
-        'LSHIFTA', 'RSHIFTA', 'LSHIFT', 'RSHIFT', 
+        'LSHIFTA', 'RSHIFTA', 'LSHIFT', 'RSHIFT',
         'LT', 'GT', 'LE', 'GE', 'EQ', 'NE', 'EQL', 'NEL',
         'COND', # ?
         'EQUALS',
@@ -78,7 +81,7 @@ def token(self):
         'INTNUMBER_OCT', 'SIGNED_INTNUMBER_OCT',
         'INTNUMBER_BIN', 'SIGNED_INTNUMBER_BIN',
         'LPAREN','RPAREN', 'LBRACKET', 'RBRACKET', 'LBRACE', 'RBRACE',
-        'DELAY', 'DOLLER', 
+        'DELAY', 'DOLLER',
         )
 
     skipped = (
@@ -188,7 +191,7 @@ def t_COMMENTOUT(self, t):
     octal_escape = r"""([0-7]{1,3})"""
     hex_escape = r"""(x[0-9a-fA-F]+)"""
     escape_sequence = r"""(\\("""+simple_escape+'|'+octal_escape+'|'+hex_escape+'))'
-    string_char = r"""([^"\\\n]|"""+escape_sequence+')'    
+    string_char = r"""([^"\\\n]|"""+escape_sequence+')'
     string_literal = '"'+string_char+'*"'
 
     identifier = r"""(([a-zA-Z_])([a-zA-Z_0-9$])*)|((\\\S)(\S)*)"""
@@ -201,38 +204,38 @@ def t_STRING_LITERAL(self, t):
     def t_FLOATNUMBER(self, t):
         return t
 
-    @TOKEN(bin_number)
-    def t_INTNUMBER_BIN(self, t):
-        return t
-
     @TOKEN(signed_bin_number)
     def t_SIGNED_INTNUMBER_BIN(self, t):
         return t
 
-    @TOKEN(octal_number)
-    def t_INTNUMBER_OCT(self, t):
+    @TOKEN(bin_number)
+    def t_INTNUMBER_BIN(self, t):
         return t
 
     @TOKEN(signed_octal_number)
     def t_SIGNED_INTNUMBER_OCT(self, t):
         return t
 
-    @TOKEN(hex_number)
-    def t_INTNUMBER_HEX(self, t):
-         return t
+    @TOKEN(octal_number)
+    def t_INTNUMBER_OCT(self, t):
+        return t
 
     @TOKEN(signed_hex_number)
     def t_SIGNED_INTNUMBER_HEX(self, t):
          return t
 
-    @TOKEN(decimal_number)
-    def t_INTNUMBER_DEC(self, t):
-        return t
+    @TOKEN(hex_number)
+    def t_INTNUMBER_HEX(self, t):
+         return t
 
     @TOKEN(signed_decimal_number)
     def t_SIGNED_INTNUMBER_DEC(self, t):
         return t
 
+    @TOKEN(decimal_number)
+    def t_INTNUMBER_DEC(self, t):
+        return t
+
     @TOKEN(identifier)
     def t_ID(self, t):
         t.type = self.reserved.get(t.value, 'ID')
@@ -258,7 +261,7 @@ def _find_tok_column(self, token):
             if self.lexer.lexdata[i] == '\n': break
             i -= 1
         return (token.lexpos - i) + 1
-    
+
     def _make_tok_location(self, token):
         return (token.lineno, self._find_tok_column(token))