Redundant deepcopy is removed by performance reason

Author: shtaxxx

pyverilog/controlflow/controlflow_analyzer.py

@@ -309,6 +309,10 @@ def showVersion():
                          default=False,help="Non graph generation")
     optparser.add_option("--nolabel",action="store_true",dest="nolabel",
                          default=False,help="State Machine Graph without Labels")
+    optparser.add_option("-I","--include",dest="include",action="append",
+                         default=[],help="Include path")
+    optparser.add_option("-D",dest="define",action="append",
+                         default=[],help="Macro Definition")
     (options, args) = optparser.parse_args()
 
     filelist = args
@@ -321,7 +325,9 @@ def showVersion():
     if len(filelist) == 0:
         showVersion()
 
-    analyzer = VerilogDataflowAnalyzer(filelist, options.topmodule)
+    analyzer = VerilogDataflowAnalyzer(filelist, options.topmodule,
+                                       preprocess_include=options.include,
+                                       preprocess_define=options.define)
     analyzer.generate()
 
     directives = analyzer.get_directives()

pyverilog/dataflow/dataflow_analyzer.py

@@ -12,6 +12,7 @@
 import subprocess
 
 sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) )
+sys.setrecursionlimit(16 * 1024)
 
 import pyverilog
 import pyverilog.utils
@@ -28,12 +29,16 @@
     from bindvisitor import BindVisitor
 
 class VerilogDataflowAnalyzer(VerilogCodeParser):
-    def __init__(self, filelist, topmodule='TOP', noreorder=False, nobind=False):
+    def __init__(self, filelist, topmodule='TOP', noreorder=False, nobind=False,
+                 preprocess_include=None,
+                 preprocess_define=None):
         self.topmodule = topmodule
         self.terms = {}
         self.binddict = {}
         self.frametable = None
-        VerilogCodeParser.__init__(self, filelist)
+        VerilogCodeParser.__init__(self, filelist,
+                                   preprocess_include=preprocess_include,
+                                   preprocess_define=preprocess_define)
         self.noreorder = noreorder
         self.nobind = nobind
 
@@ -106,6 +111,10 @@ def showVersion():
                          default=False,help="No binding traversal, Default=False")
     optparser.add_option("--noreorder",action="store_true",dest="noreorder",
                          default=False,help="No reordering of binding dataflow, Default=False")
+    optparser.add_option("-I","--include",dest="include",action="append",
+                         default=[],help="Include path")
+    optparser.add_option("-D",dest="define",action="append",
+                         default=[],help="Macro Definition")
     (options, args) = optparser.parse_args()
 
     filelist = args
@@ -119,8 +128,10 @@ def showVersion():
         showVersion()
 
     verilogdataflowanalyzer = VerilogDataflowAnalyzer(filelist, options.topmodule,
-                                                          noreorder=options.noreorder,
-                                                          nobind=options.nobind)
+                                                      noreorder=options.noreorder,
+                                                      nobind=options.nobind,
+                                                      preprocess_include=options.include,
+                                                      preprocess_define=options.define)
     verilogdataflowanalyzer.generate()
 
     directives = verilogdataflowanalyzer.get_directives()

pyverilog/dataflow/visit.py

@@ -354,14 +354,14 @@ def getModuleName(self):
     ############################################################################
     def setBlockingAssign(self, dst, bind):
         if not dst in self.blockingassign:
-            self.blockingassign[dst] = (copy.deepcopy(bind),)
+            self.blockingassign[dst] = (bind,)
             return
         current = self.blockingassign[dst]
         for c_i, c in enumerate(current):
             if c.msb == bind.msb and c.msb == bind.msb and c.ptr == bind.ptr:
-                self.blockingassign[dst][c_i].tree = copy.deepcopy(bind.tree)
+                self.blockingassign[dst][c_i].tree = bind.tree
                 return
-        self.blockingassign[dst] = current + (copy.deepcopy(bind),)
+        self.blockingassign[dst] = current + (bind,)
 
     def getBlockingAssign(self, dst):
         if dst in self.blockingassign: return self.blockingassign[dst]

pyverilog/vparser/parser.py

@@ -1730,7 +1730,9 @@ def showVersion():
     if len(filelist) == 0:
         showVersion()
 
-    codeparser = VerilogCodeParser(filelist, preprocess_include=options.include, preprocess_define=options.define)
+    codeparser = VerilogCodeParser(filelist, 
+                                   preprocess_include=options.include,
+                                   preprocess_define=options.define)
     ast = codeparser.parse()
     directives = codeparser.get_directives()