operator percedence fix according to latest IEEE verilog document - https://www.eg.bucknell.edu/~csci320/2016-fall/wp-content/uploads/2015/08/verilog-std-1364-2005.pdf

Author: tomchean

pyverilog/utils/op2mark.py

@@ -33,10 +33,11 @@ def op2mark(op):
     'Sll':4, 'Srl':4, 'Sla':4, 'Sra':4,
     'LessThan':5, 'GreaterThan':5, 'LessEq':5, 'GreaterEq':5,
     'Eq':6, 'NotEq':6, 'Eql':6, 'NotEql':6,
-    'And':7, 'Xor':7, 'Xnor':7,
-    'Or':8,
-    'Land':9,
-    'Lor':10
+    'And':7,
+    'Xor':8, 'Xnor':8,
+    'Or':9,
+    'Land':10,
+    'Lor':11
     }
 
 def op2order(op):

pyverilog/vparser/parser.py

@@ -36,7 +36,8 @@ class VerilogParser(PLYParser):
         ('left', 'LOR'),
         ('left', 'LAND'),
         ('left', 'OR'),
-        ('left', 'AND', 'XOR', 'XNOR'),
+        ('left', 'XOR', 'XNOR'),
+        ('left', 'AND'),
         ('left', 'EQ', 'NE', 'EQL', 'NEL'),
         ('left', 'LT', 'GT', 'LE', 'GE'),
         ('left', 'LSHIFT', 'RSHIFT', 'LSHIFTA', 'RSHIFTA'),