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‎README.md‎

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@@ -22,7 +22,7 @@ What's Pyverilog?
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Pyverilog is open-source hardware design processing toolkit for Verilog HDL.
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All source codes are written in Python.
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Pyverilog includes (1) code parser, (2) dataflow analyzer, (3) control-flow analyzer and (4) code generator.
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Pyverilog includes **(1) code parser, (2) dataflow analyzer, (3) control-flow analyzer and (4) code generator**.
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You can create your own design analyzer, code translator and code generator of Verilog HDL based on this toolkit.
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- apt-get install iverilog
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Getting Started
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Functions
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------------------------------
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This software includes various tools for Verilog HDL design.
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* controlflow: Control-flow analyzer with condition analyzer that identify when a signal is activated.
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* ast\_code\_generator: Verilog HDL code generator from AST.
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To use them, please type 'make' in each sub directory.
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Getting Started
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------------------------------
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First, please prepare a Verilog HDL source file as below. The file name is 'test.v'.
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This sample design adds the input value internally whtn the enable signal is asserted. Then is outputs its partial value to the LED.
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```verilog
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module top
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(
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input CLK,
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input RST,
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input enable,
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input [31:0] value,
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output [7:0] led
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);
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reg [31:0] count;
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reg [7:0] state;
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assign led = count[23:16];
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always @(posedge CLK) begin
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if(RST) begin
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count <= 0;
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state <= 0;
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end else begin
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if(state == 0) begin
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if(enable) state <= 1;
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end else if(state == 1) begin
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state <= 2;
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end else if(state == 2) begin
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count <= count + value;
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state <= 0;
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end
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end
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end
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endmodule
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```
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**Code parser**
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Let's try syntax analysis. Please type the command as below.
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```
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python3.3 pyverilog/vparser/parser.py test.v
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```
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Then you got the result as below. The result of syntax analysis is displayed.
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```
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Source:
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Description:
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ModuleDef: top
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Paramlist:
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Portlist:
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Ioport:
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Input: CLK, False
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Width:
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IntConst: 0
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IntConst: 0
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Ioport:
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Input: RST, False
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Width:
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IntConst: 0
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IntConst: 0
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Ioport:
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Input: enable, False
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Width:
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IntConst: 0
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IntConst: 0
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Ioport:
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Input: value, False
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Width:
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IntConst: 31
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IntConst: 0
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Ioport:
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Output: led, False
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Width:
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IntConst: 7
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IntConst: 0
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Decl:
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Reg: count, False
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Width:
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IntConst: 31
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IntConst: 0
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Decl:
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Reg: state, False
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Width:
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IntConst: 7
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IntConst: 0
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Assign:
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Lvalue:
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Identifier: led
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Rvalue:
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Partselect:
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Identifier: count
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IntConst: 23
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IntConst: 16
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Always:
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SensList:
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Sens: posedge
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Identifier: CLK
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Block: None
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IfStatement:
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Identifier: RST
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Block: None
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NonblockingSubstitution:
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Lvalue:
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Identifier: count
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Rvalue:
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IntConst: 0
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NonblockingSubstitution:
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Lvalue:
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Identifier: state
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Rvalue:
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IntConst: 0
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Block: None
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IfStatement:
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Eq:
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Identifier: state
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IntConst: 0
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Block: None
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IfStatement:
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Identifier: enable
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NonblockingSubstitution:
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Lvalue:
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Identifier: state
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Rvalue:
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IntConst: 1
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IfStatement:
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Eq:
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Identifier: state
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IntConst: 1
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Block: None
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NonblockingSubstitution:
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Lvalue:
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Identifier: state
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Rvalue:
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IntConst: 2
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IfStatement:
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Eq:
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Identifier: state
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IntConst: 2
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Block: None
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NonblockingSubstitution:
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Lvalue:
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Identifier: count
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Rvalue:
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Plus:
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Identifier: count
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Identifier: value
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NonblockingSubstitution:
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Lvalue:
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Identifier: state
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Rvalue:
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IntConst: 0
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```
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**Dataflow analyzer**
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Let's try dataflow analysis. Please type the command as below.
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```
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python3.3 pyverilog/dataflow/dataflow_analyzer.py -t top test.v
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```
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Then you got the result as below. The result of each signal definition and each signal assignment are displayed.
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```
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Directive:
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Instance:
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(top, 'top')
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Term:
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(Term name:top.led type:{'Output'} msb:(IntConst 7) lsb:(IntConst 0))
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(Term name:top.enable type:{'Input'} msb:(IntConst 0) lsb:(IntConst 0))
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(Term name:top.CLK type:{'Input'} msb:(IntConst 0) lsb:(IntConst 0))
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(Term name:top.count type:{'Reg'} msb:(IntConst 31) lsb:(IntConst 0))
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(Term name:top.state type:{'Reg'} msb:(IntConst 7) lsb:(IntConst 0))
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(Term name:top.RST type:{'Input'} msb:(IntConst 0) lsb:(IntConst 0))
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(Term name:top.value type:{'Input'} msb:(IntConst 31) lsb:(IntConst 0))
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Bind:
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(Bind dest:top.count tree:(Branch Cond:(Terminal top.RST) True:(IntConst 0) False:(Branch Cond:(Operator Eq Next:(Terminal top.state),(IntConst 0)) False:(Branch Cond:(Operator Eq Next:(Terminal top.state),(IntConst 1)) False:(Branch Cond:(Operator Eq Next:(Terminal top.state),(IntConst 2)) True:(Operator Plus Next:(Terminal top.count),(Terminal top.value)))))))
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(Bind dest:top.state tree:(Branch Cond:(Terminal top.RST) True:(IntConst 0) False:(Branch Cond:(Operator Eq Next:(Terminal top.state),(IntConst 0)) True:(Branch Cond:(Terminal top.enable) True:(IntConst 1)) False:(Branch Cond:(Operator Eq Next:(Terminal top.state),(IntConst 1)) True:(IntConst 2) False:(Branch Cond:(Operator Eq Next:(Terminal top.state),(IntConst 2)) True:(IntConst 0))))))
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(Bind dest:top.led tree:(Partselect Var:(Terminal top.count) MSB:(IntConst 23) LSB:(IntConst 16)))
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```
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Let's view the result of dataflow analysis as a picture file. Now we select 'led' as the target. Please type the command as below.
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```
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python3.3 pyverilog/dataflow/graphgen.py -t top -s top.led test.v
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```
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Then you got a png file (out.png). The picture shows that the definition of 'led' is a part-selection of 'count' from 23-bit to 16-bit.
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![out.png](http://cdn-ak.f.st-hatena.com/images/fotolife/s/sxhxtxa/20140101/20140101045641.png)
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**Control-flow analyzer**
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Let's try control-flow analysis. Please type the command as below.
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```
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python2.7 pyverilog/controlflow/controlflow_analyzer.py -t top test.v
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```
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Then you got the result as below. The result shows that the state machine structure and transition conditions to the next state in the state machine.
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```
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FSM signal: top.count, Condition list length: 4
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FSM signal: top.state, Condition list length: 5
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Condition: (Ulnot, Eq), Inferring transition condition
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Condition: (Eq, top.enable), Inferring transition condition
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Condition: (Ulnot, Ulnot, Eq), Inferring transition condition
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# SIGNAL NAME: top.state
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# DELAY CNT: 0
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0 --(top_enable>'d0)--> 1
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1 --None--> 2
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2 --None--> 0
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Loop
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(0, 1, 2)
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```
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You got also a png file (top_state.png). The picture shows that the graphical structure of the state machine.
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![top_state.png](http://cdn-ak.f.st-hatena.com/images/fotolife/s/sxhxtxa/20140101/20140101045835.png)
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**Code generator**
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Finally, let's try code generation. Please prepare a Python script as below. The file name is 'test.py'.
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A Verilog HDL code is represented by using the AST classes defined in 'vparser.ast'.
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```python
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import pyverilog.vparser.ast as vast
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from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
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params = vast.Paramlist(())
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clk = vast.Ioport( vast.Input('CLK') )
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rst = vast.Ioport( vast.Input('RST') )
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width = vast.Width( vast.IntConst('7'), vast.IntConst('0') )
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led = vast.Ioport( vast.Output('led', width=width) )
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ports = vast.Portlist( (clk, rst, led) )
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items = ( vast.Assign( vast.Identifier('led'), vast.IntConst('8') ) ,)
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ast = vast.ModuleDef("top", params, ports, items)
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codegen = ASTCodeGenerator()
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rslt = codegen.visit(ast)
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print(rslt)
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```
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Please type the command as below at the same directory with Pyverilog.
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```
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python3.3 test.py
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```
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Then Verilog HDL code generated from the AST instances is displayed.
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```verilog
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module top
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(
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input [0:0] CLK,
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input [0:0] RST,
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output [7:0] led
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);
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assign led = 8;
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endmodule
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```
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Related Project and Site
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------------------------------
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[PyCoRAM](http://shtaxxx.github.io/PyCoRAM/)
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- Python-based Implementation of CoRAM Memory Architecture for AXI4 Interconnection on FPGAs
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[shtaxxx.hatenablog.com](http://shtaxxx.hatenablog.com/entry/2014/01/01/045856)
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- Blog entry for introduction and examples of Pyverilog (in Japansese)
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