We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
1 parent e0f1e68 commit b138f7bCopy full SHA for b138f7b
pyverilog/ast_code_generator/codegen.py
@@ -1019,3 +1019,6 @@ def visit_SingleStatement(self, node):
1019
}
1020
rslt = template.render(template_dict)
1021
return rslt
1022
+
1023
+ def visit_EmbeddedCode(self, node):
1024
+ return self.indent(node.code)
pyverilog/vparser/ast.py
@@ -832,3 +832,11 @@ def children(self):
832
nodelist = []
833
if self.statement: nodelist.append(self.statement)
834
return tuple(nodelist)
835
836
+class EmbeddedCode(Node):
837
+ attr_names = ('code',)
838
+ def __init__(self, code, lineno=0):
839
+ self.code = code
840
+ def children(self):
841
+ nodelist = []
842
+ return tuple(nodelist)
0 commit comments