erge branch 'feature_contribution' into develop

Author: shtaxxx

README.md

@@ -5,7 +5,7 @@ Pyverilog
 
 Python-based Hardware Design Processing Toolkit for Verilog HDL
 
-Copyright 2013, Shinya Takamaeda-Yamazaki
+Copyright 2013, Shinya Takamaeda-Yamazaki and Contributors
 
 
 License
@@ -50,6 +50,20 @@ Pyverilog includes **(1) code parser, (2) dataflow analyzer, (3) control-flow an
 You can create your own design analyzer, code translator and code generator of Verilog HDL based on this toolkit.
 
 
+Contribute to Pyverilog
+==============================
+
+Pyverilog project always welcomes questions, bug reports, feature proposals, and pull requests on GitHub.
+
+Pyverilog uses pytest for the integration testing. When you send a pull request, please include a test example with pytest.
+
+
+Documentation
+==============================
+
+To be described.
+
+
 Installation
 ==============================
 

README.rst

@@ -5,7 +5,7 @@ Pyverilog
 
 Python-based Hardware Design Processing Toolkit for Verilog HDL
 
-Copyright 2013, Shinya Takamaeda-Yamazaki
+Copyright 2013, Shinya Takamaeda-Yamazaki and Contributors
 
 License
 =======
@@ -53,6 +53,20 @@ control-flow analyzer and (4) code generator**. You can create your own
 design analyzer, code translator and code generator of Verilog HDL based
 on this toolkit.
 
+Contribute to Pyverilog
+=======================
+
+Pyverilog project always welcomes questions, bug reports, feature
+proposals, and pull requests on GitHub.
+
+Pyverilog uses pytest for the integration testing. When you send a pull
+request, please include a test example with pytest.
+
+Documentation
+=============
+
+To be described.
+
 Installation
 ============