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Merge branch 'pull-request-master'
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+225
-60
lines changed

7 files changed

+225
-60
lines changed

‎pyverilog/dataflow/dataflow.py‎

Lines changed: 18 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,10 @@
11
#-------------------------------------------------------------------------------
22
# dataflow.py
3-
#
3+
#
44
# Basic classes of Data flow nodes
55
#
66
# Copyright (C) 2013, Shinya Takamaeda-Yamazaki
7+
# modified by ryoduke fukatani
78
# License: Apache 2.0
89
#-------------------------------------------------------------------------------
910

@@ -47,7 +48,7 @@ def __repr__(self): pass
4748
def tostr(self): pass
4849
def tocode(self, dest='dest'): return self.__repr__()
4950
def tolabel(self): return self.__repr__()
50-
def children(self):
51+
def children(self):
5152
nodelist = []
5253
return tuple(nodelist)
5354
def __eq__(self, other):
@@ -69,8 +70,8 @@ def __repr__(self):
6970
return ret[:-1]
7071
def tostr(self):
7172
ret = '(Terminal '
72-
for n in self.name:
73-
ret += str(n) + '.'
73+
for n in self.name:
74+
ret += str(n) + '.'
7475
return ret[0:-1] + ')'
7576
def tocode(self, dest='dest'):
7677
#ret = ''
@@ -207,7 +208,7 @@ def __eq__(self, other):
207208
return self.operator == other.operator and self.nextnodes == other.nextnodes
208209
def __hash__(self):
209210
return hash((self.operator, tuple(self.nextnodes)))
210-
211+
211212
class DFPartselect(DFNotTerminal):
212213
attr_names = ()
213214
def __init__(self, var, msb, lsb):
@@ -312,8 +313,8 @@ def __repr__(self):
312313
return 'Branch'
313314
def tostr(self):
314315
ret = '(Branch'
315-
if self.condnode is not None: ret += ' Cond:' + self.condnode.tostr()
316-
if self.truenode is not None: ret += ' True:' + self.truenode.tostr()
316+
if self.condnode is not None: ret += ' Cond:' + self.condnode.tostr()
317+
if self.truenode is not None: ret += ' True:' + self.truenode.tostr()
317318
if self.falsenode is not None: ret += ' False:'+ self.falsenode.tostr()
318319
ret += ')'
319320
return ret
@@ -334,15 +335,15 @@ def _tocode_always(self, dest='dest', always='clockedge'):
334335
ret = 'if('
335336
if self.condnode is not None: ret += self.condnode.tocode(dest)
336337
ret += ') begin\n'
337-
if self.truenode is not None:
338+
if self.truenode is not None:
338339
if isinstance(self.truenode, DFBranch):
339340
ret += self.truenode.tocode(dest, always=always)
340341
elif always == 'clockedge':
341342
ret += dest + ' <= ' + self.truenode.tocode(dest) + ';\n'
342343
elif always == 'combination':
343344
ret += dest + ' = ' + self.truenode.tocode(dest) + ';\n'
344345
ret += 'end\n'
345-
if self.falsenode is not None:
346+
if self.falsenode is not None:
346347
ret += 'else begin\n'
347348
if isinstance(self.falsenode, DFBranch):
348349
ret += self.falsenode.tocode(dest, always=always)
@@ -462,7 +463,7 @@ def __repr__(self):
462463
return 'Delay'
463464
def tostr(self):
464465
ret = '(Delay '
465-
if self.nextnode is not None: ret += self.nextnode.tostr()
466+
if self.nextnode is not None: ret += self.nextnode.tostr()
466467
ret += ')'
467468
return ret
468469
def tocode(self, dest='dest'):
@@ -522,8 +523,8 @@ def __repr__(self):
522523
return str(self.name)
523524
def tostr(self):
524525
ret = '(Term name:' + str(self.name) + ' type:' + str(self.termtype)
525-
if self.msb is not None: ret += ' msb:' + self.msb.tostr()
526-
if self.lsb is not None: ret += ' lsb:' + self.lsb.tostr()
526+
if self.msb is not None: ret += ' msb:' + self.msb.tostr()
527+
if self.lsb is not None: ret += ' lsb:' + self.lsb.tostr()
527528
if self.lenmsb is not None: ret += ' lenmsb:' + self.lenmsb.tostr()
528529
if self.lenlsb is not None: ret += ' lenlsb:' + self.lenlsb.tostr()
529530
ret += ')'
@@ -641,7 +642,7 @@ def _localparam(self):
641642
code = 'localparam ' + dest
642643
code += ' = ' + self.tree.tocode(dest) + ';\n'
643644
return code
644-
645+
645646
def _assign(self):
646647
dest = self.getdest()
647648
code = 'assign ' + dest
@@ -652,10 +653,10 @@ def _always_clockedge(self):
652653
dest = self.getdest()
653654
code = 'always @('
654655
if self.alwaysinfo.clock_edge is not None and self.alwaysinfo.clock_name is not None:
655-
code += self.alwaysinfo.clock_edge + ' '
656+
code += self.alwaysinfo.clock_edge + ' '
656657
code += util.toFlatname(self.alwaysinfo.clock_name)
657658
if self.alwaysinfo.reset_edge is not None and self.alwaysinfo.reset_name is not None:
658-
code += ' or '
659+
code += ' or '
659660
code += self.alwaysinfo.reset_edge + ' '
660661
code += util.toFlatname(self.alwaysinfo.reset_name)
661662
code += ') begin\n'
@@ -681,7 +682,7 @@ def _always_combination(self):
681682
code += 'end\n'
682683
code += '\n'
683684
return code
684-
685+
685686
def isClockEdge(self):
686687
if self.alwaysinfo is None: return False
687688
return self.alwaysinfo.isClockEdge()
@@ -752,7 +753,7 @@ def setBind(self, name, bind):
752753
currentbindlist = self.binddict[name]
753754
c_i = 0
754755
for c in currentbindlist:
755-
if c.msb == bind.msb and c.msb == bind.msb and c.ptr == bind.ptr:
756+
if c.msb == bind.msb and c.lsb == bind.lsb and c.ptr == bind.ptr:
756757
self.binddict[name][c_i].tree = bind.tree
757758
return
758759
c_i += 1

‎pyverilog/testcode/casex.v‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,24 @@
1+
module TOP(CLK, RST, LED);
2+
input CLK, RST;
3+
output [7:0] LED;
4+
reg [7:0] cnt;
5+
always @(posedge CLK) begin
6+
if(RST) begin
7+
cnt <= 0;
8+
end else begin
9+
casex(cnt)
10+
'b00: begin
11+
cnt <= cnt + 1;
12+
end
13+
'b1x: begin
14+
cnt <= 0;
15+
end
16+
default: begin
17+
cnt <= cnt + 1;
18+
end
19+
endcase
20+
end
21+
end
22+
assign LED = cnt;
23+
endmodule
24+

‎pyverilog/testcode/signed.v‎

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,18 @@
1+
//`default_nettype none
2+
3+
module TOP(CLK, RST);
4+
input CLK, RST;
5+
reg [7:0] cnt;
6+
7+
8+
always @(posedge CLK or negedge RST) begin
9+
if(RST) begin
10+
cnt <= 'd0;
11+
end else begin
12+
cnt <= cnt + 1'sd1;
13+
end
14+
end
15+
16+
17+
endmodule
18+

‎pyverilog/testcode/test_sd.py‎

Lines changed: 108 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,108 @@
1+
#-------------------------------------------------------------------------------
2+
# test_sd.py
3+
#
4+
# Lexical analyzer
5+
#
6+
# Copyright (C) 2015, ryosuke fukatani
7+
# License: Apache 2.0
8+
#-------------------------------------------------------------------------------
9+
10+
11+
import sys
12+
import os
13+
import subprocess
14+
15+
sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) )
16+
17+
from pyverilog.dataflow.dataflow_analyzer import *
18+
import unittest
19+
20+
21+
class TestSequenceFunctions(unittest.TestCase):
22+
def setUp(self):
23+
path_clone = sys.path
24+
pop_target = []
25+
for i,path in enumerate(path_clone):
26+
if path == 'C:\\Python27\\lib\\site-packages\\pyverilog-0.9.0-py2.7.egg':
27+
pop_target.append(i)
28+
for i in reversed(pop_target):
29+
sys.path.pop(i)
30+
reload(pyverilog.dataflow.dataflow_analyzer)
31+
32+
def test_signed(self):
33+
terms, binddict = self.dataflow_wrapper("signed.v")
34+
self.assertEqual(binddict.values()[0][0].tostr(),
35+
"(Bind dest:TOP.cnt tree:(Branch Cond:(Terminal TOP.RST) True:(IntConst 'd0) False:(Operator Plus Next:(Terminal TOP.cnt),(IntConst 1'sd1))))")
36+
37+
def test_casex(self):
38+
self.dataflow_wrapper("casex.v")
39+
40+
def dataflow_wrapper(self,code_file):
41+
42+
from optparse import OptionParser
43+
44+
optparser = OptionParser()
45+
optparser.add_option("-v","--version",action="store_true",dest="showversion",
46+
default=False,help="Show the version")
47+
optparser.add_option("-I","--include",dest="include",action="append",
48+
default=[],help="Include path")
49+
optparser.add_option("-D",dest="define",action="append",
50+
default=[],help="Macro Definition")
51+
optparser.add_option("-t","--top",dest="topmodule",
52+
default="TOP",help="Top module, Default=TOP")
53+
optparser.add_option("--nobind",action="store_true",dest="nobind",
54+
default=False,help="No binding traversal, Default=False")
55+
optparser.add_option("--noreorder",action="store_true",dest="noreorder",
56+
default=False,help="No reordering of binding dataflow, Default=False")
57+
58+
filelist = {code_file}
59+
options = optparser.get_default_values()
60+
61+
62+
for f in filelist:
63+
if not os.path.exists(f): raise IOError("file not found: " + f)
64+
65+
verilogdataflowanalyzer = VerilogDataflowAnalyzer(filelist, options.topmodule,
66+
noreorder=options.noreorder,
67+
nobind=options.nobind,
68+
preprocess_include=options.include,
69+
preprocess_define=options.define)
70+
verilogdataflowanalyzer.generate()
71+
72+
directives = verilogdataflowanalyzer.get_directives()
73+
print('Directive:')
74+
for dr in directives:
75+
print(dr)
76+
77+
instances = verilogdataflowanalyzer.getInstances()
78+
print('Instance:')
79+
for ins in instances:
80+
print(ins)
81+
82+
if options.nobind:
83+
print('Signal:')
84+
signals = verilogdataflowanalyzer.getSignals()
85+
for sig in signals:
86+
print(sig)
87+
88+
print('Const:')
89+
consts = verilogdataflowanalyzer.getConsts()
90+
for con in consts:
91+
print(con)
92+
93+
else:
94+
terms = verilogdataflowanalyzer.getTerms()
95+
print('Term:')
96+
for tk, tv in sorted(terms.items(), key=lambda x:len(x[0])):
97+
print(tv.tostr())
98+
99+
binddict = verilogdataflowanalyzer.getBinddict()
100+
print('Bind:')
101+
for bk, bv in sorted(binddict.items(), key=lambda x:len(x[0])):
102+
for bvi in bv:
103+
print(bvi.tostr())
104+
105+
return terms, binddict
106+
107+
if __name__ == '__main__':
108+
unittest.main()

‎pyverilog/vparser/ast.py‎

Lines changed: 10 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,10 @@
11
#-------------------------------------------------------------------------------
22
# ast.py
3-
#
3+
#
44
# Verilog HDL AST classes with Pyverilog
55
#
66
# Copyright (C) 2013, Shinya Takamaeda-Yamazaki
7+
# edited by ryosuke fukatani
78
# License: Apache 2.0
89
#-------------------------------------------------------------------------------
910

@@ -47,7 +48,7 @@ def __hash__(self):
4748
s = hash(tuple([getattr(self, a) for a in self.attr_names]))
4849
c = hash(self.children())
4950
return hash((s, c))
50-
51+
5152
################################################################################
5253
class Source(Node):
5354
attr_names = ('name',)
@@ -171,7 +172,7 @@ def children(self):
171172
nodelist = []
172173
if self.width: nodelist.append(self.width)
173174
return tuple(nodelist)
174-
175+
175176
class Input(Variable): pass
176177
class Output(Variable): pass
177178
class Inout(Variable): pass
@@ -347,11 +348,11 @@ class Power(Operator): pass
347348
class Times(Operator): pass
348349
class Divide(Operator): pass
349350
class Mod(Operator): pass
350-
################################################################################
351+
################################################################################
351352
# Level 3
352353
class Plus(Operator): pass
353354
class Minus(Operator): pass
354-
################################################################################
355+
################################################################################
355356
# Level 4
356357
class Sll(Operator): pass
357358
class Srl(Operator): pass
@@ -510,6 +511,8 @@ def children(self):
510511
if self.caselist: nodelist.extend(self.caselist)
511512
return tuple(nodelist)
512513

514+
class CasexStatement(CaseStatement): pass
515+
513516
class Case(Node):
514517
attr_names = ()
515518
def __init__(self, cond, statement):
@@ -540,7 +543,7 @@ def children(self):
540543
if self.statement: nodelist.append(self.statement)
541544
return tuple(nodelist)
542545

543-
class EventStatement(Node):
546+
class EventStatement(Node):
544547
attr_names = ()
545548
def __init__(self, senslist):
546549
self.senslist = senslist
@@ -589,7 +592,7 @@ def children(self):
589592
if self.parameterlist: nodelist.extend(self.parameterlist)
590593
if self.instances: nodelist.extend(self.instances)
591594
return tuple(nodelist)
592-
595+
593596
class Instance(Node):
594597
attr_names = ('name', 'module')
595598
def __init__(self, module, name, portlist, parameterlist, array=None):

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