Parse rule of variable without width is modified. The previous implementation appends [0:0] as implicit data width for variables without width field. The current implementation appends None instead of [0:0]. Analysis rule in dataflow is modified as well.

Author: shtaxxx

pyverilog/dataflow/bindvisitor.py

@@ -807,8 +807,8 @@ def searchTaskPorts(self, name, scope):
     def makeConstantTerm(self, name, node, scope):
         termtype = node.__class__.__name__
         termtypes = set([termtype])
-        msb = DFEvalValue(31) if node.width is None else self.makeDFTree(node.width.msb, scope)
-        lsb = DFEvalValue(0) if node.width is None else self.makeDFTree(node.width.lsb, scope)
+        msb = DFIntConst('31') if node.width is None else self.makeDFTree(node.width.msb, scope)
+        lsb = DFIntConst('0') if node.width is None else self.makeDFTree(node.width.lsb, scope)
         return Term(name, termtypes, msb, lsb)
 
     def addTerm(self, node, rscope=None):
@@ -821,8 +821,12 @@ def addTerm(self, node, rscope=None):
         if self.frames.isTaskcall(): termtype = 'Task'
         termtypes = set([termtype])
 
-        msb = DFEvalValue(31) if node.width is None else self.makeDFTree(node.width.msb, scope)
-        lsb = DFEvalValue(0) if node.width is None else self.makeDFTree(node.width.lsb, scope)
+        if isinstance(node, (Parameter, Localparam)):
+            msb = DFIntConst('31') if node.width is None else self.makeDFTree(node.width.msb, scope)
+        else:
+            msb = DFIntConst('0') if node.width is None else self.makeDFTree(node.width.msb, scope)
+        lsb = DFIntConst('0') if node.width is None else self.makeDFTree(node.width.lsb, scope)
+        
         lenmsb = None
         lenlsb = None
         if isinstance(node, RegArray) or isinstance(node, WireArray):

pyverilog/dataflow/signalvisitor.py

@@ -477,8 +477,8 @@ def searchConstantValue(self, key, name):
     def makeConstantTerm(self, name, node, scope):
         termtype = node.__class__.__name__
         termtypes = set([termtype])
-        msb = DFEvalValue(31) if node.width is None else self.makeDFTree(node.width.msb, scope)
-        lsb = DFEvalValue(0) if node.width is None else self.makeDFTree(node.width.lsb, scope)
+        msb = DFIntConst('31') if node.width is None else self.makeDFTree(node.width.msb, scope)
+        lsb = DFIntConst('0') if node.width is None else self.makeDFTree(node.width.lsb, scope)
         return Term(name, termtypes, msb, lsb)
 
     def getTree(self, node, scope):

pyverilog/vparser/ast.py

@@ -166,7 +166,7 @@ class Variable(Value):
     attr_names = ('name', 'signed')
     def __init__(self, name, width=None, signed=False):
         self.name = name
-        self.width = width if width else Width(IntConst('0'),IntConst('0'))
+        self.width = width
         self.signed = signed
     def children(self):
         nodelist = []
@@ -223,7 +223,7 @@ class Parameter(Node):
     def __init__(self, name, value, width=None, signed=False):
         self.name = name
         self.value = value
-        self.width = width #if width else Width(msb=IntConst('31'),lsb=IntConst('0'))
+        self.width = width
         self.signed = signed
     def children(self):
         nodelist = []

pyverilog/vparser/parser.py

@@ -272,7 +272,6 @@ def p_ioports_one(self, p):
         p[0] = (p[1],)
 
     def ioport_create(self, sigtypes, name, width=None):
-        width = Width(IntConst('0'),IntConst('0')) if width is None else width
         self.ioport_typecheck(sigtypes)
         first = None
         second = None
@@ -377,7 +376,6 @@ def p_standard_item(self, p):
 
     # Signal Decl
     def decl_create(self, sigtypes, name, width=None, length=None):
-        width = Width(msb=IntConst('0'), lsb=IntConst('0')) if width is None else width
         self.decl_typecheck(sigtypes, length)
         decls = []
         signed = False
@@ -465,7 +463,6 @@ def p_declarray(self, p):
 
     # Decl and Assign
     def declassign_create(self, sigtypes, name, assign, width=None):
-        width = Width(msb=IntConst('0'), lsb=IntConst('0')) if width is None else width
         self.declassign_typecheck(sigtypes)
         decls = []
         signed = False

tests/dataflow_test/test_led.py

@@ -12,7 +12,7 @@
 (Term name:led.CLK type:['Input'] msb:(IntConst 0) lsb:(IntConst 0))
 (Term name:led.LED type:['Output', 'Reg'] msb:(IntConst 7) lsb:(IntConst 0))
 (Term name:led.RST type:['Input'] msb:(IntConst 0) lsb:(IntConst 0))
-(Term name:led.STEP type:['Parameter'] msb:'d31 lsb:'d0)
+(Term name:led.STEP type:['Parameter'] msb:(IntConst 31) lsb:(IntConst 0))
 (Term name:led.count type:['Reg'] msb:(IntConst 31) lsb:(IntConst 0))
 Bind:
 (Bind dest:led.LED tree:(Branch Cond:(Terminal led.RST) True:(IntConst 0) False:(Branch Cond:(Operator Eq Next:(Terminal led.count),(Operator Minus Next:(Terminal led.STEP),(IntConst 1))) True:(Operator Plus Next:(Terminal led.LED),(IntConst 1)))))

tests/parser_test/test_delay.py

@@ -21,14 +21,8 @@
       Portlist: 
         Ioport: 
           Input: CLK, False
-            Width: 
-              IntConst: 0
-              IntConst: 0
         Ioport: 
           Input: RST, False
-            Width: 
-              IntConst: 0
-              IntConst: 0
         Ioport: 
           Output: LED, False
             Width: 

tests/parser_test/test_escape.py

@@ -20,18 +20,9 @@
         Port: \\1234RST*%&, None
       Decl: 
         Input: \\CLK~, False
-          Width: 
-            IntConst: 0
-            IntConst: 0
         Input: \\1234RST*%&, False
-          Width: 
-            IntConst: 0
-            IntConst: 0
       Decl: 
         Output: LE$D, False
-          Width: 
-            IntConst: 0
-            IntConst: 0
       Decl: 
         Genvar: i, False
           Width: 

tests/parser_test/test_instance_array.py

@@ -37,19 +37,10 @@
               IntConst: 0
         Ioport: 
           Input: in3, False
-            Width: 
-              IntConst: 0
-              IntConst: 0
         Ioport: 
           Input: in4, False
-            Width: 
-              IntConst: 0
-              IntConst: 0
         Ioport: 
           Input: in5, False
-            Width: 
-              IntConst: 0
-              IntConst: 0
         Ioport: 
           Output: LED0, False
             Width: 
@@ -72,14 +63,8 @@
               IntConst: 0
         Ioport: 
           Output: LED4, False
-            Width: 
-              IntConst: 0
-              IntConst: 0
         Ioport: 
           Output: LED5, False
-            Width: 
-              IntConst: 0
-              IntConst: 0
       InstanceList: SUB
         ParamArg: MODE
           IntConst: 0
@@ -191,14 +176,8 @@
       Portlist: 
         Ioport: 
           Input: VAL, False
-            Width: 
-              IntConst: 0
-              IntConst: 0
         Ioport: 
           Output: LED, False
-            Width: 
-              IntConst: 0
-              IntConst: 0
       Assign: 
         Lvalue: 
           Identifier: LED

tests/parser_test/test_led_main.py

@@ -21,14 +21,8 @@
       Portlist: 
         Ioport: 
           Input: CLK, False
-            Width: 
-              IntConst: 0
-              IntConst: 0
         Ioport: 
           Input: RST, False
-            Width: 
-              IntConst: 0
-              IntConst: 0
         Ioport: 
           Output: LED, False
             Width: 
@@ -94,14 +88,8 @@
       Portlist: 
         Ioport: 
           Input: CLK, False
-            Width: 
-              IntConst: 0
-              IntConst: 0
         Ioport: 
           Input: RST, False
-            Width: 
-              IntConst: 0
-              IntConst: 0
         Ioport: 
           Output: LED, False
             Width: