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Fixed a bug of delay statement
1 parent b4b08e0 commit a209fd3

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5 files changed

+24
-32
lines changed

5 files changed

+24
-32
lines changed

testcode/test.v

Lines changed: 7 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -1,37 +1,16 @@
1-
module TOP(CLK, RST_X, IN, OUT);
2-
input CLK, RST_X;
3-
input [7:0] IN;
4-
output [7:0] OUT;
51

6-
reg [7:0] state;
7-
reg [7:0] nstate;
2+
module TOP(CLK, RST, LED);
3+
input CLK, RST;
4+
output [7:0] LED;
85
reg [7:0] cnt;
9-
10-
integer i;
11-
12-
parameter W_DIR = 5;
13-
parameter W_FLIT = 8;
14-
15-
function isvalid;
16-
input [W_FLIT-1:0] in;
17-
isvalid = in[W_FLIT-1];
18-
endfunction
19-
20-
always @* begin
21-
nstate = 0;
22-
if( !(isvalid(nstate)) )
23-
nstate = nstate + 1;
24-
end
25-
6+
localparam DELAYSIZE = 5;
267
always @(posedge CLK) begin
27-
if(!RST_X) begin
28-
state <= 0;
8+
if(RST) begin
299
cnt <= 0;
3010
end else begin
31-
state <= nstate;
32-
cnt <= cnt + 1;
11+
cnt <= #DELAYSIZE cnt==255? 0 : cnt + 1;
3312
end
3413
end
35-
14+
assign LED = cnt;
3615
endmodule
3716

vparser/Makefile

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,8 @@ PREPROCESS=preprocessor.py
55
LEXER=lexer.py
66
PARSER=parser.py
77

8-
SRCS=../testcode/generate.v
8+
SRCS=../testcode/test.v
9+
#SRCS=../testcode/generate.v
910

1011
.PHONY: parse
1112
parse:

vparser/lexer.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -262,7 +262,7 @@ def my_error_func(msg, a, b):
262262
sys.write(msg + "\n")
263263
sys.exit()
264264

265-
filename = '../test/generate.v'
265+
filename = '../testcode/test.v'
266266
text = open(filename, 'r').read()
267267

268268
lexer = VerilogLexer(error_func = my_error_func)

vparser/parser.py

Lines changed: 13 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1073,9 +1073,21 @@ def p_nonblocking_substitution(self, p):
10731073

10741074
######################################################################
10751075
def p_delays(self, p):
1076-
"""delays : DELAY expression"""
1076+
"""delays : DELAY LPAREN expression RPAREN"""
1077+
p[0] = DelayStatement(p[3])
1078+
1079+
def p_delays_identifier(self, p):
1080+
"""delays : DELAY identifier"""
10771081
p[0] = DelayStatement(p[2])
10781082

1083+
def p_delays_intnumber(self, p):
1084+
"""delays : DELAY intnumber"""
1085+
p[0] = DelayStatement(IntConst(p[2]))
1086+
1087+
def p_delays_floatnumber(self, p):
1088+
"""delays : DELAY floatnumber"""
1089+
p[0] = DelayStatement(FloatConst(p[2]))
1090+
10791091
def p_delays_empty(self, p):
10801092
"""delays : empty"""
10811093
p[0] = None

vparser/preprocessor.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,7 @@ def preprocess(self):
4040
subprocess.call(cmd, shell=True)
4141

4242
if __name__ == '__main__':
43-
filelist = ('../test/generate.v',)
43+
filelist = ('../testcode/test.v',)
4444
pp_outputfile = 'pp.out'
4545
vp = VerilogPreprocessor(filelist, pp_outputfile, include=('./'))
4646
vp.preprocess()

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