Merge pull request #50 from efabless/develop

Added a number of configuration options

Author: shtaxxx

pyverilog/vparser/parser.py

@@ -18,6 +18,7 @@
 from __future__ import print_function
 import sys
 import os
+import pathlib
 
 from pyverilog.vparser.ply.yacc import yacc
 from pyverilog.vparser.plyparser import PLYParser, Coord, ParseError
@@ -48,14 +49,18 @@ class VerilogParser(PLYParser):
         # -> Strong
     )
 
-    def __init__(self):
+    def __init__(self, outputdir=".", debug=True):
         self.lexer = VerilogLexer(error_func=self._lexer_error_func)
         self.lexer.build()
 
         self.tokens = self.lexer.tokens
-        #self.parser = yacc(module=self)
-        # Use this if you want to build the parser using LALR(1) instead of SLR
-        self.parser = yacc(module=self, method="LALR")
+        pathlib.Path(outputdir).mkdir(parents=True, exist_ok=True)
+        self.parser = yacc(
+            module=self,
+            method="LALR",
+            outputdir=outputdir,
+            debug=debug
+        )
 
     def _lexer_error_func(self, msg, line, column):
         self._parse_error(msg, self._coord(line, column))
@@ -2243,13 +2248,16 @@ class VerilogCodeParser(object):
 
     def __init__(self, filelist, preprocess_output='preprocess.output',
                  preprocess_include=None,
-                 preprocess_define=None):
+                 preprocess_define=None,
+                 outputdir=".",
+                 debug=True
+                 ):
         self.preprocess_output = preprocess_output
         self.directives = ()
         self.preprocessor = VerilogPreprocessor(filelist, preprocess_output,
                                                 preprocess_include,
                                                 preprocess_define)
-        self.parser = VerilogParser()
+        self.parser = VerilogParser(outputdir=outputdir, debug=debug)
 
     def preprocess(self):
         self.preprocessor.preprocess()
@@ -2267,10 +2275,20 @@ def get_directives(self):
         return self.directives
 
 
-def parse(filelist, preprocess_include=None, preprocess_define=None):
-    codeparser = VerilogCodeParser(filelist,
-                                   preprocess_include=preprocess_include,
-                                   preprocess_define=preprocess_define)
+def parse(
+    filelist,
+    preprocess_include=None,
+    preprocess_define=None,
+    outputdir=".",
+    debug=True
+):
+    codeparser = VerilogCodeParser(
+        filelist,
+        preprocess_include=preprocess_include,
+        preprocess_define=preprocess_define,
+        outputdir=outputdir,
+        debug=debug
+    )
     ast = codeparser.parse()
     directives = codeparser.get_directives()
     return ast, directives

pyverilog/vparser/preprocessor.py

@@ -30,31 +30,30 @@
 class VerilogPreprocessor(object):
     def __init__(self, filelist, outputfile='pp.out', include=None, define=None):
         self.filelist = filelist
-        cmd = []
-        cmd.append('iverilog ')
-        if include:
-            for inc in include:
-                cmd.append('-I ')
-                cmd.append(inc)
-                cmd.append(' ')
-        if define:
-            for d in define:
-                cmd.append('-D')
-                cmd.append(d)
-                cmd.append(' ')
-        cmd.append('-E -o ')
-        cmd.append(outputfile)
-        self.iv = ''.join(cmd)
+        iverilog_invocable = os.environ.get("PYVERILOG_IVERILOG") or "iverilog"
+        include = include or []
+        define = define or []
+        includes = map(
+            lambda includable: "-I '{0}'".format(includable), include
+        )
+        defines = map(lambda definable: "-D {0}".format(definable), define)
+        self.iv = "'{0}' {1} {2} -E -o '{3}'".format(
+            iverilog_invocable, ' '.join(includes), ' '.join(defines),
+            outputfile
+        )
 
     def preprocess(self):
-        cmd = self.iv + ' '
-        for f in self.filelist:
-            cmd += ' ' + f
+        files = map(lambda file: "'{0}'".format(file), self.filelist)
+        cmd = "{0} {1}".format(self.iv, ' '.join(files))
         subprocess.call(cmd, shell=True)
 
 
-def preprocess(filelist,
-               output='preprocess.output', include=None, define=None):
+def preprocess(
+    filelist,
+    output='preprocess.output',
+    include=None,
+    define=None
+):
     pre = VerilogPreprocessor(filelist, output, include, define)
     pre.preprocess()
     text = open(output).read()