Merge branch 'master' of https://github.com/fukatani/Pyverilog-1 into work

Conflicts:
	pyverilog/testcode/test_sd.py

Author: fukatani

pyverilog/ast_code_generator/codegen.py

@@ -66,11 +66,12 @@ def visit_Description(self, node):
     def visit_ModuleDef(self, node):
         filename = getfilename(node)
         template = self.env.get_template(filename)
-        paramlist = self.visit(node.paramlist)
+        paramlist = self.visit(node.paramlist) if node.paramlist is not None else ''
+        portlist = self.visit(node.portlist) if node.portlist is not None else ''
         template_dict = {
             'modulename' : escape(node.name),
-            'paramlist' : '' if len(node.paramlist.params) == 0 else paramlist,
-            'portlist' : self.visit(node.portlist),
+            'paramlist' : paramlist,
+            'portlist' :  portlist,
             'items' : [ self.visit(item) for item in node.items ],
             }
         rslt = template.render(template_dict)

pyverilog/dataflow/bindvisitor.py

@@ -4,6 +4,7 @@
 # Binding visitor
 #
 # Copyright (C) 2013, Shinya Takamaeda-Yamazaki
+# edited by ryosuke fukatani
 # License: Apache 2.0
 #-------------------------------------------------------------------------------
 
@@ -233,12 +234,12 @@ def visit_Always(self, node):
                                       generate=self.frames.isGenerate(),
                                       always=True)
 
-        (clock_name, clock_edge,
-         reset_name, reset_edge,
+        (clock_name, clock_edge, clock_bit,
+         reset_name, reset_edge, reset_bit,
          senslist) = self._createAlwaysinfo(node, current)
 
-        self.frames.setAlwaysInfo(clock_name, clock_edge,
-                                  reset_name, reset_edge, senslist)
+        self.frames.setAlwaysInfo(clock_name, clock_edge, clock_bit,
+                                  reset_name, reset_edge, reset_bit, senslist)
 
         self.generic_visit(node)
         self.frames.setCurrent(current)
@@ -257,19 +258,28 @@ def _createAlwaysinfo(self, node, scope):
         senslist = []
         clock_edge = None
         clock_name = None
+        clock_bit = None
         reset_edge = None
         reset_name = None
+        reset_bit = None
 
         for l in node.sens_list.list:
             if l.sig is None:
                 continue
-            signame = self._get_signal_name(l.sig)
+            if isinstance(l.sig, pyverilog.vparser.ast.Pointer):
+                signame = self._get_signal_name(l.sig.var)
+                bit = int(l.sig.ptr.value)
+            else:
+                signame = self._get_signal_name(l.sig)
+                bit = 0
             if signaltype.isClock(signame):
-                clock_name = self.searchTerminal(l.sig.name, scope)
+                clock_name = self.searchTerminal(signame, scope)
                 clock_edge = l.type
+                clock_bit = bit
             elif signaltype.isReset(signame):
-                reset_name = self.searchTerminal(l.sig.name, scope)
+                reset_name = self.searchTerminal(signame, scope)
                 reset_edge = l.type
+                reset_bit = bit
             else:
                 senslist.append(l)
 
@@ -278,7 +288,7 @@ def _createAlwaysinfo(self, node, scope):
         if reset_edge is not None and len(senslist) > 0:
             raise verror.FormatError('Illegal sensitivity list')
 
-        return (clock_name, clock_edge, reset_name, reset_edge, senslist)
+        return (clock_name, clock_edge, clock_bit, reset_name, reset_edge, reset_bit, senslist)
 
     def visit_IfStatement(self, node):
         if self.frames.isFunctiondef() and not self.frames.isFunctioncall(): return

pyverilog/dataflow/dataflow.py

@@ -692,12 +692,18 @@ def getClockName(self):
     def getClockEdge(self):
         if self.alwaysinfo is None: return ''
         return self.alwaysinfo.getClockEdge()
+    def getClockBit(self):
+        if self.alwaysinfo is None: return ''
+        return self.alwaysinfo.getClockBit()
     def getResetName(self):
         if self.alwaysinfo is None: return ''
         return self.alwaysinfo.getResetName()
     def getResetEdge(self):
         if self.alwaysinfo is None: return ''
         return self.alwaysinfo.getResetEdge()
+    def getResetBit(self):
+        if self.alwaysinfo is None: return ''
+        return self.alwaysinfo.getResetBit()
     def getSenslist(self):
         if self.alwaysinfo is None: return ''
         return self.alwaysinfo.getSenslist()

pyverilog/dataflow/visit.py

@@ -54,21 +54,27 @@ def generic_visit(self, node):
 # Signal/Object Management Classes
 ################################################################################
 class AlwaysInfo(object):
-    def __init__(self, clock_name='', clock_edge=None,
-                 reset_name='', reset_edge=None, senslist=()):
+    def __init__(self, clock_name='', clock_edge=None, clock_bit=0,
+                 reset_name='', reset_edge=None, reset_bit=0, senslist=()):
         self.clock_name = clock_name
         self.clock_edge = clock_edge
+        self.clock_bit = clock_bit
         self.reset_name = reset_name
         self.reset_edge = reset_edge
+        self.reset_bit = reset_bit
         self.senslist = senslist
     def getClockName(self):
         return self.clock_name
     def getClockEdge(self):
         return self.clock_edge
+    def getClockBit(self):
+        return self.clock_bit
     def getResetName(self):
         return self.reset_name
     def getResetEdge(self):
         return self.reset_edge
+    def getResetBit(self):
+        return self.reset_bit
     def isClockEdge(self):
         if self.clock_name != '' and self.clock_edge == 'posedge': return True
         if self.clock_name != '' and self.clock_edge == 'negedge': return True
@@ -316,10 +322,10 @@ def isInitial(self):
     def setNext(self, nextframe):
         self.next.append(nextframe)
 
-    def setAlwaysInfo(self, clock_name, clock_edge, 
-                      reset_name, reset_edge, senslist):
-        self.alwaysinfo = AlwaysInfo(clock_name, clock_edge,
-                                     reset_name, reset_edge, senslist)        
+    def setAlwaysInfo(self, clock_name, clock_edge, clock_bit,
+                      reset_name, reset_edge, reset_bit, senslist):
+        self.alwaysinfo = AlwaysInfo(clock_name, clock_edge, clock_bit,
+                                     reset_name, reset_edge, reset_bit, senslist)
 
     def addSignal(self, node):
         self.variables.addSignal(node.name, node)
@@ -415,10 +421,10 @@ def toScopeChain(self, scopename):
         if scopename is None: return self.current
         return self.current + scopename
 
-    def addFrame(self, scopename, 
-                 frametype='none', 
-                 alwaysinfo=None, condition=None, 
-                 module=False, functioncall=False, taskcall=False, 
+    def addFrame(self, scopename,
+                 frametype='none',
+                 alwaysinfo=None, condition=None,
+                 module=False, functioncall=False, taskcall=False,
                  generate=False, always=False, initial=False, loop=None, loop_iter=None,
                  modulename=None):
 
@@ -429,10 +435,10 @@ def addFrame(self, scopename,
         previous = self.current
         if len(previous) > 0:
             self.dict[previous].setNext(scopechain)
-        self.dict[scopechain] = Frame(scopechain, previous, frametype=frametype, 
-                                      alwaysinfo=alwaysinfo, condition=condition, 
-                                      module=module, functioncall=functioncall, 
-                                      taskcall=taskcall, generate=generate, 
+        self.dict[scopechain] = Frame(scopechain, previous, frametype=frametype,
+                                      alwaysinfo=alwaysinfo, condition=condition,
+                                      module=module, functioncall=functioncall,
+                                      taskcall=taskcall, generate=generate,
                                       always=always, initial=initial, loop=loop, loop_iter=loop_iter,
                                       modulename=modulename)
         self.current = scopechain
@@ -496,10 +502,10 @@ def setForIter(self, iter):
     def getForIter(self):
         return self.for_iter
 
-    def setAlwaysInfo(self, clock_name, clock_edge, 
-                      reset_name, reset_edge, senslist):
-        self.dict[self.current].setAlwaysInfo(clock_name, clock_edge, 
-                                              reset_name, reset_edge, senslist)
+    def setAlwaysInfo(self, clock_name, clock_edge, clock_bit,
+                      reset_name, reset_edge, reset_bit, senslist):
+        self.dict[self.current].setAlwaysInfo(clock_name, clock_edge, clock_bit,
+                                              reset_name, reset_edge, reset_bit, senslist)
 
     def setCurrent(self, current):
         self.current = current

pyverilog/testcode/ptr_clock_reset.v

@@ -0,0 +1,17 @@
+//`default_nettype none
+
+module TOP(CLK,RST);
+  input [3:1] CLK;
+  input [1:0] RST;
+  reg cnt;
+
+
+  always @(posedge CLK[2] or posedge RST[0]) begin
+    if(RST[0]) begin
+      cnt <= 'd0;
+    end
+  end
+
+endmodule
+
+

pyverilog/testcode/test_sd.py

@@ -40,12 +40,17 @@ def test_signed_task(self):
     def test_casex(self):
         self.dataflow_wrapper("casex.v")
 
+    def test_ptr_clock_reset(self):
+        terms, binddict = self.dataflow_wrapper("ptr_clock_reset.v")
+        self.assertEqual(binddict.values()[0][0].getClockBit(), 2)
+        self.assertEqual(binddict.values()[0][0].getResetBit(), 0)
+
     def test_decimal(self):
         terms, binddict = self.dataflow_wrapper("decimal.v")
         self.assertEqual(binddict.values()[0][0].tostr(),
         "(Bind dest:TOP.cnt1 tree:(Branch Cond:(Terminal TOP.RST) True:(IntConst 'd0) False:(Operator Plus Next:(Terminal TOP.cnt1),(IntConst 8'd1))))")
 
-    def test_decimal2(self):
+    def test_ptr_clock_reset(self):
         terms, binddict = self.dataflow_wrapper("decimal2.v")
         self.assertEqual(binddict.values()[0][0].tostr(),
         "(Bind dest:TOP.cnt2 tree:(Branch Cond:(Terminal TOP.RST) True:(IntConst 'd0) False:(Operator Plus Next:(Terminal TOP.cnt2),(IntConst 'd1))))")