Merge branch 'develop'

Author: shtaxxx

CONTRIBUTORS.md

@@ -1,4 +1,4 @@
-Main Committer
+Main Committers
 ====================
 
 - Shinya Takamaeda-Yamazaki (@shtaxxx)

README.md

@@ -5,7 +5,7 @@ Pyverilog
 
 Python-based Hardware Design Processing Toolkit for Verilog HDL
 
-Copyright 2013, Shinya Takamaeda-Yamazaki
+Copyright 2013, Shinya Takamaeda-Yamazaki and Contributors
 
 
 License
@@ -19,7 +19,7 @@ Note that this software package includes PLY-3.4 in "vparser/ply". The license o
 Publication
 ==============================
 
-If you use Pyverilog in your research, please cite my paper.
+If you use Pyverilog in your research, please cite the following paper.
 
 - Shinya Takamaeda-Yamazaki: Pyverilog: A Python-based Hardware Design Processing Toolkit for Verilog HDL, 11th International Symposium on Applied Reconfigurable Computing (ARC 2015) (Poster), Lecture Notes in Computer Science, Vol.9040/2015, pp.451-460, April 2015.
 [Paper](http://link.springer.com/chapter/10.1007/978-3-319-16214-0_42)
@@ -50,6 +50,31 @@ Pyverilog includes **(1) code parser, (2) dataflow analyzer, (3) control-flow an
 You can create your own design analyzer, code translator and code generator of Verilog HDL based on this toolkit.
 
 
+Contribute to Pyverilog
+==============================
+
+Pyverilog project always welcomes questions, bug reports, feature proposals, and pull requests on [GitHub](https://github.com/PyHDI/Pyverilog).
+
+### for questions, bug reports, and feature proposals
+
+Please leave your comment on the [issue tracker](https://github.com/PyHDI/Pyverilog/issues) on GitHub.
+
+### for pull requests
+
+Please check "CONTRIBUTORS.md" for the contributors who provided pull requests.
+
+Pyverilog uses **pytest** for the integration testing. **When you send a pull request, please include a testing example with pytest.** 
+To write a testing code, please refer the existing testing examples in "tests" directory.
+
+If the requested codes passes the testing successfully and have no obvious problem, they will be merged to the *develop* branch by the main committers.
+
+
+Documentation
+==============================
+
+To be described.
+
+
 Installation
 ==============================
 

README.rst

@@ -5,7 +5,7 @@ Pyverilog
 
 Python-based Hardware Design Processing Toolkit for Verilog HDL
 
-Copyright 2013, Shinya Takamaeda-Yamazaki
+Copyright 2013, Shinya Takamaeda-Yamazaki and Contributors
 
 License
 =======
@@ -18,7 +18,7 @@ license of PLY is BSD.
 Publication
 ===========
 
-If you use Pyverilog in your research, please cite my paper.
+If you use Pyverilog in your research, please cite the following paper.
 
 -  Shinya Takamaeda-Yamazaki: Pyverilog: A Python-based Hardware Design
    Processing Toolkit for Verilog HDL, 11th International Symposium on
@@ -53,6 +53,39 @@ control-flow analyzer and (4) code generator**. You can create your own
 design analyzer, code translator and code generator of Verilog HDL based
 on this toolkit.
 
+Contribute to Pyverilog
+=======================
+
+Pyverilog project always welcomes questions, bug reports, feature
+proposals, and pull requests on
+`GitHub <https://github.com/PyHDI/Pyverilog>`__.
+
+for questions, bug reports, and feature proposals
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Please leave your comment on the `issue
+tracker <https://github.com/PyHDI/Pyverilog/issues>`__ on GitHub.
+
+for pull requests
+~~~~~~~~~~~~~~~~~
+
+Please check “CONTRIBUTORS.md” for the contributors who provided pull
+requests.
+
+Pyverilog uses **pytest** for the integration testing. **When you send a
+pull request, please include a testing example with pytest.** To write a
+testing code, please refer the existing testing examples in “tests”
+directory.
+
+If the requested codes passes the testing successfully and have no
+obvious problem, they will be merged to the *develop* branch by the main
+committers.
+
+Documentation
+=============
+
+To be described.
+
 Installation
 ============