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always_latch support
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pyverilog/vparser/ast.py

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@@ -742,6 +742,10 @@ class AlwaysComb(Always):
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pass
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class AlwaysLatch(Always):
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pass
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class SensList(Node):
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attr_names = ()
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pyverilog/vparser/parser.py

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@@ -473,6 +473,7 @@ def p_standard_item(self, p):
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| always
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| always_ff
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| always_comb
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| always_latch
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| initial
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| instance
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| function
@@ -1273,10 +1274,17 @@ def p_always(self, p):
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def p_always_ff(self, p):
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'always_ff : ALWAYS_FF senslist always_statement'
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p[0] = AlwaysFF(p[2], p[3], lineno=p.lineno(1))
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p.set_lineno(0, p.lineno(1))
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def p_always_comb(self, p):
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'always_comb : ALWAYS_COMB senslist always_statement'
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p[0] = AlwaysComb(p[2], p[3], lineno=p.lineno(1))
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p.set_lineno(0, p.lineno(1))
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def p_always_latch(self, p):
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'always_latch : ALWAYS_LATCH senslist always_statement'
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p[0] = AlwaysLatch(p[2], p[3], lineno=p.lineno(1))
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p.set_lineno(0, p.lineno(1))
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def p_sens_egde_paren(self, p):
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'senslist : AT LPAREN edgesigs RPAREN'

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