We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
1 parent 4cf11b2 commit 8d90018Copy full SHA for 8d90018
pyverilog/ast_code_generator/codegen.py
@@ -460,11 +460,15 @@ def visit_Operator(self, node):
460
left = self.visit(node.left)
461
right = self.visit(node.right)
462
if ( isinstance(node.left, (Identifier, Value)) or
463
- ((not isinstance(node.left, (Sll, Srl, Sra))) and
+ ((not isinstance(node.left, (Sll, Srl, Sra,
464
+ LessThan, GreaterThan, LessEq, GreaterEq,
465
+ Eq, NotEq, Eql, NotEql))) and
466
(lorder is not None and lorder <= order)) ):
467
left = del_paren(left)
468
if ( isinstance(node.right, (Identifier, Value)) or
- ((not isinstance(node.right, (Sll, Srl, Sra))) and
469
+ ((not isinstance(node.right, (Sll, Srl, Sra,
470
471
472
(rorder is not None and order > rorder)) ):
473
right = del_paren(right)
474
template_dict = {
0 commit comments