Extend all port decls to be n-d arrays

All port declarations can now be declared as n-d arrays (with arbitrary
number of dimensions).

Author: Rajsekhar Setaluri

pyverilog/ast_code_generator/codegen.py

@@ -371,7 +371,8 @@ def visit_Ioport(self, node):
             'second': '' if node.second is None else node.second.__class__.__name__.lower(),
             'name': escape(node.first.name),
             'width': '' if node.first.width is None else self.visit(node.first.width),
-            'signed': node.first.signed or (node.second is not None and node.second.signed)
+            'signed': node.first.signed or (node.second is not None and node.second.signed),
+            'dimensions': '' if node.first.dimensions is None else self.visit(node.first.dimensions)
         }
         rslt = template.render(template_dict)
         return rslt

pyverilog/ast_code_generator/template/ioport.txt

@@ -1 +1 @@
-{{ first }} {% if second != '' %}{{ second }} {% endif %}{% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }}
+{{ first }} {% if second != '' %}{{ second }} {% endif %}{% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }}{% if dimensions != '' %} {{ dimensions }}{% endif %}

pyverilog/vparser/parser.py

@@ -365,26 +365,25 @@ def p_ioports_one(self, p):
         p[0] = (p[1],)
         p.set_lineno(0, p.lineno(1))
 
-    def create_ioport(self, sigtypes, name, width=None, lineno=0):
+    def create_ioport(self, sigtypes, name, width=None, dimensions=None, lineno=0):
         self.typecheck_ioport(sigtypes)
         first = None
         second = None
         signed = False
         if 'signed' in sigtypes:
             signed = True
         if 'input' in sigtypes:
-            first = Input(name=name, width=width, signed=signed, lineno=lineno)
+            first = Input(name=name, width=width, signed=signed, dimensions=dimensions, lineno=lineno)
         if 'output' in sigtypes:
-            first = Output(name=name, width=width,
-                           signed=signed, lineno=lineno)
+            first = Output(name=name, width=width, signed=signed, dimensions=dimensions, lineno=lineno)
         if 'inout' in sigtypes:
-            first = Inout(name=name, width=width, signed=signed, lineno=lineno)
+            first = Inout(name=name, width=width, signed=signed, dimensions=dimensions, lineno=lineno)
         if 'wire' in sigtypes:
-            second = Wire(name=name, width=width, signed=signed, lineno=lineno)
+            second = Wire(name=name, width=width, signed=signed, dimensions=dimensions, lineno=lineno)
         if 'reg' in sigtypes:
-            second = Reg(name=name, width=width, signed=signed, lineno=lineno)
+            second = Reg(name=name, width=width, signed=signed, dimensions=dimensions, lineno=lineno)
         if 'tri' in sigtypes:
-            second = Tri(name=name, width=width, signed=signed, lineno=lineno)
+            second = Tri(name=name, width=width, signed=signed, dimensions=dimensions, lineno=lineno)
         return Ioport(first, second, lineno=lineno)
 
     def typecheck_ioport(self, sigtypes):
@@ -415,6 +414,11 @@ def p_ioport_width(self, p):
         p[0] = self.create_ioport(p[1], p[3], width=p[2], lineno=p.lineno(3))
         p.set_lineno(0, p.lineno(1))
 
+    def p_ioport_dimensions(self, p):
+        'ioport : sigtypes width portname dimensions'
+        p[0] = self.create_ioport(p[1], p[3], width=p[2], dimensions=p[4], lineno=p.lineno(3))
+        p.set_lineno(0, p.lineno(1))
+
     def p_ioport_head(self, p):
         'ioport_head : sigtypes portname'
         p[0] = self.create_ioport(p[1], p[2], lineno=p.lineno(2))
@@ -425,6 +429,11 @@ def p_ioport_head_width(self, p):
         p[0] = self.create_ioport(p[1], p[3], width=p[2], lineno=p.lineno(3))
         p.set_lineno(0, p.lineno(1))
 
+    def p_ioport_head_dimensions(self, p):
+        'ioport_head : sigtypes width portname dimensions'
+        p[0] = self.create_ioport(p[1], p[3], width=p[2], dimensions=p[4], lineno=p.lineno(3))
+        p.set_lineno(0, p.lineno(1))
+
     def p_ioport_portname(self, p):
         'ioport : portname'
         p[0] = p[1]