controlflow_analyzer.py is updated: user-defined FSM name is supported.

Author: shtaxxx

pyverilog/controlflow/controlflow_analyzer.py

@@ -342,9 +342,10 @@ def showVersion():
     resolved_terms = optimizer.getResolvedTerms()
     resolved_binddict = optimizer.getResolvedBinddict()
     constlist = optimizer.getConstlist()
-
+    fsm_vars = tuple(['fsm', 'state', 'count', 'cnt', 'step', 'mode'] + options.searchtarget)
+    
     canalyzer = VerilogControlflowAnalyzer(options.topmodule, terms, binddict,
-                                          resolved_terms, resolved_binddict, constlist)
+                                           resolved_terms, resolved_binddict, constlist, fsm_vars)
     fsms = canalyzer.getFiniteStateMachines()
 
     for signame, fsm in fsms.items():