setup.py is updated for the dependency attributes.

Author: shtaxxx

README.md

@@ -51,32 +51,33 @@ Pyverilog includes **(1) code parser, (2) dataflow analyzer, (3) control-flow an
 You can create your own design analyzer, code translator and code generator of Verilog HDL based on this toolkit.
 
 
-Software Requirements
+Installation
 ==============================
 
-* Python (2.7, 3.3 or later)
-* Icarus Verilog (0.9.6 or later)
-   - pyverilog.vparser.preprocessor.py uses 'iverilog -E' command as the preprocessor.
-   - 'apt-get install iverilog'
-* Graphviz and Pygraphviz (Python3 does not support Pygraphviz)
-   - pyverilog.dataflow.graphgen and pyverilog.controlflow.controlflow (without --nograph option) use Pygraphviz (on Python 2.7).
-   - If you do not use graphgen and controlflow (without --nograph) option, Python 3.x is fine.
-* Jinja2 (2.7 or later)
-   - ast\_code\_generator requires jinja2 module.
-   - 'pip3 install jinja2' (for Python 3.x) or 'pip install jinja2' (for Python 2.7)
+Software Requirements
+--------------------
 
+- Python: 2.7, 3.4 or later
 
-Installation
-==============================
+- Icarus Verilog: 0.9.7 or later
 
-If you want to use Pyverilog as a general library, you can install on your environment by using setup.py.
-If Python 2.7 is used,
+Install on your platform. For exmple, on Ubuntu:
 
-    python setup.py install
+    sudo apt-get install iverilog
+
+- Jinja2: 2.8 or later
+- pytest: 2.8.2 or later
+- pytest-pythonpath: 0.7 or lator
+- Pygraphviz: 1.3.1 or later (Option for graph visualization in dataflow/graphgen.py and controlflow/controlflow_analyzer.py)
+
+Install on your python environment by using pip.
 
-If Python 3.x is used,
+    pip install jinja2 pytest pytest-pythonpath
+    (pip install pygraphviz) # option
 
-    python3 setup.py install
+Finally, install Pyverilog.
+
+    python setup.py install
 
 
 Tools

README.rst

@@ -53,39 +53,40 @@ control-flow analyzer and (4) code generator**. You can create your own
 design analyzer, code translator and code generator of Verilog HDL based
 on this toolkit.
 
-Software Requirements
-=====================
-
--  Python (2.7, 3.3 or later)
--  Icarus Verilog (0.9.6 or later)
--  pyverilog.vparser.preprocessor.py uses 'iverilog -E' command as the
-   preprocessor.
--  'apt-get install iverilog'
--  Graphviz and Pygraphviz (Python3 does not support Pygraphviz)
--  pyverilog.dataflow.graphgen and pyverilog.controlflow.controlflow
-   (without --nograph option) use Pygraphviz (on Python 2.7).
--  If you do not use graphgen and controlflow (without --nograph)
-   option, Python 3.x is fine.
--  Jinja2 (2.7 or later)
--  ast\_code\_generator requires jinja2 module.
--  'pip3 install jinja2' (for Python 3.x) or 'pip install jinja2' (for
-   Python 2.7)
-
 Installation
 ============
 
-If you want to use Pyverilog as a general library, you can install on
-your environment by using setup.py. If Python 2.7 is used,
+Software Requirements
+---------------------
+
+-  Python: 2.7, 3.4 or later
+
+-  Icarus Verilog: 0.9.7 or later
+
+Install on your platform. For exmple, on Ubuntu:
 
 ::
 
-    python setup.py install
+    sudo apt-get install iverilog
+
+-  Jinja2: 2.8 or later
+-  pytest: 2.8.2 or later
+-  pytest-pythonpath: 0.7 or lator
+-  Pygraphviz: 1.3.1 or later (Option for graph visualization in
+   dataflow/graphgen.py and controlflow/controlflow\_analyzer.py)
 
-If Python 3.x is used,
+Install on your python environment by using pip.
 
 ::
 
-    python3 setup.py install
+    pip install jinja2 pytest pytest-pythonpath
+    (pip install pygraphviz) # option
+
+Finally, install Pyverilog.
+
+::
+
+    python setup.py install
 
 Tools
 =====

pyverilog/ast_code_generator/Makefile

@@ -1,4 +1,5 @@
 PYTHON=python3
+#PYTHON=python
 #OPT=-m pdb
 #OPT=-m cProfile -s time
 #OPT=-m cProfile -o profile.rslt

pyverilog/controlflow/Makefile

@@ -1,5 +1,5 @@
 PYTHON=python3
-#PYTHON=python2.7
+#PYTHON=python
 #OPT=-m pdb
 #OPT=-m cProfile -s time
 #OPT=-m cProfile -o profile.rslt

pyverilog/controlflow/controlflow_analyzer.py

@@ -4,7 +4,6 @@
 # Controlflow analyzer 
 #
 # for visualization, graphviz and pygraphviz are required
-# (only Python 2.7 is supported)
 #
 # Copyright (C) 2013, Shinya Takamaeda-Yamazaki
 # License: Apache 2.0
@@ -205,9 +204,9 @@ def view(self):
                 print(''.join(s))
 
     def tograph(self, filename='fsm.png', nolabel=False):
-        import pygraphviz as pgv # Python 3 currently does not support Pygraphviz
-
-        graph = pgv.AGraph(directed=True) #pgv.AGraph(strict=False, directed=True)
+        import pygraphviz as pgv
+        #graph = pgv.AGraph(strict=False, directed=True)
+        graph = pgv.AGraph(directed=True)
         for src, dstdict in self.fsm.items():
             graph.add_node(str(src), label=str(src))
             for cond, dst in dstdict.items():

pyverilog/dataflow/Makefile

@@ -1,6 +1,5 @@
 PYTHON=python3
-#PYTHON=python2.7
-PYTHON27=python2.7
+#PYTHON=python
 #OPT=-m pdb
 #OPT=-m cProfile -s time
 #OPT=-m cProfile -o profile.rslt
@@ -46,7 +45,7 @@ codegen:
 
 .PHONY: graphgen
 graphgen:
-		$(PYTHON27) $(OPT) $(GRAPHGEN) $(SRCS) $(TOP) $(TARGETS) $(GRAPHGEN_OPT)
+		$(PYTHON) $(OPT) $(GRAPHGEN) $(SRCS) $(TOP) $(TARGETS) $(GRAPHGEN_OPT)
 
 .PHONY: clean
 clean:

pyverilog/dataflow/codegen.py

@@ -170,12 +170,8 @@ def _toCode(self, terms, parameter, assign, always_clockedge, always_combination
 if __name__ == '__main__':
     from optparse import OptionParser
     import pyverilog.utils.util as util
-    if sys.version_info[0] >= 3:
-        from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
-        from pyverilog.dataflow.optimizer import VerilogDataflowOptimizer
-    else:
-        from dataflow_analyzer import VerilogDataflowAnalyzer
-        from optimizer import VerilogDataflowOptimizer
+    from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
+    from pyverilog.dataflow.optimizer import VerilogDataflowOptimizer
     INFO = "Code generator from Verilog dataflow definitions"
     VERSION = pyverilog.utils.version.VERSION
     USAGE = "Usage: python codegen.py -t TOPMODULE file ..."

pyverilog/dataflow/graphgen.py

@@ -180,12 +180,8 @@ def add_edge(self, start, end, color='black', label=None):
 if __name__ == '__main__':
     from optparse import OptionParser
     import pyverilog.utils.util as util
-    if sys.version_info[0] >= 3:
-        from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
-        from pyverilog.dataflow.optimizer import VerilogDataflowOptimizer
-    else:
-        from dataflow_analyzer import VerilogDataflowAnalyzer
-        from optimizer import VerilogDataflowOptimizer
+    from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
+    from pyverilog.dataflow.optimizer import VerilogDataflowOptimizer
     INFO = "Graph generator from dataflow"
     VERSION = pyverilog.utils.version.VERSION
     USAGE = "Usage: python graphgen.py -t TOPMODULE -s TARGETSIGNAL file ..."

pyverilog/dataflow/merge.py

@@ -497,12 +497,8 @@ def unmatchedRange(self, matched_range, search_msb, search_lsb, search_ptr):
 if __name__ == '__main__':
     from optparse import OptionParser
     import pyverilog.utils.util as util
-    if sys.version_info[0] >= 3:
-        from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
-        from pyverilog.dataflow.optimizer import VerilogDataflowOptimizer
-    else:
-        from dataflow_analyzer import VerilogDataflowAnalyzer
-        from optimizer import VerilogDataflowOptimizer
+    from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
+    from pyverilog.dataflow.optimizer import VerilogDataflowOptimizer
     INFO = "Dataflow merge module"
     VERSION = pyverilog.utils.version.VERSION
     USAGE = "Usage: python merge.py -t TOPMODULE file ..."

pyverilog/dataflow/subset.py

@@ -127,12 +127,8 @@ def _discretion(self, visited_binddict, visited_sources):
 if __name__ == '__main__':
     from optparse import OptionParser
     import pyverilog.utils.util as util
-    if sys.version_info[0] >= 3:
-        from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
-        from pyverilog.dataflow.optimizer import VerilogDataflowOptimizer
-    else:
-        from dataflow_analyzer import VerilogDataflowAnalyzer
-        from optimizer import VerilogDataflowOptimizer
+    from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
+    from pyverilog.dataflow.optimizer import VerilogDataflowOptimizer
     INFO = "Subset generator from Verilog dataflow definitions"
     VERSION = pyverilog.utils.version.VERSION
     USAGE = "Usage: python subset.py -t TOPMODULE file ..."