Preliminary support for SystemVerilog logic,always_ff,always_comb

Author: leonardt

pyverilog/vparser/ast.py

@@ -458,6 +458,12 @@ def children(self):
         if self.statement: nodelist.append(self.statement)
         return tuple(nodelist)
 
+class AlwaysFF(Always):
+    pass
+
+class AlwaysComb(Always):
+    pass
+
 class SensList(Node):
     attr_names = ()
     def __init__(self, list, lineno=0):

pyverilog/vparser/lexer.py

@@ -43,9 +43,9 @@ def token(self):
     keywords = (
         'MODULE', 'ENDMODULE', 'BEGIN', 'END', 'GENERATE', 'ENDGENERATE', 'GENVAR',
         'FUNCTION', 'ENDFUNCTION', 'TASK', 'ENDTASK',
-        'INPUT', 'INOUT', 'OUTPUT', 'TRI', 'REG', 'WIRE', 'INTEGER', 'REAL', 'SIGNED',
+        'INPUT', 'INOUT', 'OUTPUT', 'TRI', 'REG', 'LOGIC', 'WIRE', 'INTEGER', 'REAL', 'SIGNED',
         'PARAMETER', 'LOCALPARAM', 'SUPPLY0', 'SUPPLY1',
-        'ASSIGN', 'ALWAYS', 'SENS_OR', 'POSEDGE', 'NEGEDGE', 'INITIAL',
+        'ASSIGN', 'ALWAYS', 'ALWAYS_FF', 'ALWAYS_COMB', 'SENS_OR', 'POSEDGE', 'NEGEDGE', 'INITIAL',
         'IF', 'ELSE', 'FOR', 'WHILE', 'CASE', 'CASEX', 'ENDCASE', 'DEFAULT',
         'WAIT', 'FOREVER', 'DISABLE', 'FORK', 'JOIN',
         )

pyverilog/vparser/parser.py

@@ -299,6 +299,11 @@ def p_sigtype_reg(self, p):
         p[0] = p[1]
         p.set_lineno(0, p.lineno(1))
 
+    def p_sigtype_logic(self, p):
+        'sigtype : LOGIC'
+        p[0] = p[1]
+        p.set_lineno(0, p.lineno(1))
+
     def p_sigtype_wire(self, p):
         'sigtype : WIRE'
         p[0] = p[1]
@@ -458,6 +463,8 @@ def p_standard_item(self, p):
         | genvardecl
         | assignment
         | always
+        | always_ff
+        | always_comb
         | initial
         | instance
         | function
@@ -1255,6 +1262,14 @@ def p_always(self, p):
         p[0] = Always(p[2], p[3], lineno=p.lineno(1))
         p.set_lineno(0, p.lineno(1))
 
+    def p_always_ff(self, p):
+        'always_ff : ALWAYS_FF senslist always_statement'
+        p[0] = AlwaysFF(p[2], p[3], lineno=p.lineno(1))
+
+    def p_always_comb(self, p):
+        'always_comb : ALWAYS_COMB senslist always_statement'
+        p[0] = AlwaysComb(p[2], p[3], lineno=p.lineno(1))
+
     def p_sens_egde_paren(self, p):
         'senslist : AT LPAREN edgesigs RPAREN'
         p[0] = SensList(p[3], lineno=p.lineno(1))