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Merge branch 'master' of https://github.com/shtaxxx/Pyverilog 
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‎README.md‎

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@@ -348,27 +348,26 @@ python3 test.py
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Then Verilog HDL code generated from the AST instances is displayed.
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```verilog
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module top
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(
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input [0:0] CLK,
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input [0:0] RST,
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output [7:0] led
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(
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input CLK,
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input RST,
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output [7:0] led
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);
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);
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assign led = 8;
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endmodule
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endmodule
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```
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Related Project and Site
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==============================
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[Veriloggen](https://github.com/shtaxxx/veriloggen)
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[Veriloggen](https://github.com/PyHDI/veriloggen)
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- A library for constructing a Verilog HDL source code in Python
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[PyCoRAM](https://github.com/shtaxxx/PyCoRAM)
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[PyCoRAM](https://github.com/PyHDI/PyCoRAM)
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- Python-based Portable IP-core Synthesis Framework for FPGA-based Computing
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[flipSyrup](https://github.com/shtaxxx/flipSyrup)

‎README.rst‎

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.. code:: verilog
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module top
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(
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input [0:0] CLK,
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input [0:0] RST,
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output [7:0] led
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(
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input CLK,
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input RST,
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output [7:0] led
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);
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);
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assign led = 8;
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endmodule
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Related Project and Site
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========================
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`Veriloggen <https://github.com/shtaxxx/veriloggen>`__ - A library for
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`Veriloggen <https://github.com/PyHDI/veriloggen>`__ - A library for
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constructing a Verilog HDL source code in Python
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`PyCoRAM <https://github.com/shtaxxx/PyCoRAM>`__ - Python-based Portable
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`PyCoRAM <https://github.com/PyHDI/PyCoRAM>`__ - Python-based Portable
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IP-core Synthesis Framework for FPGA-based Computing
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`flipSyrup <https://github.com/shtaxxx/flipSyrup>`__ - Cycle-Accurate

‎pyverilog/__init__.py‎

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import sys
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if sys.version_info[0] < 3:
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import utils
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import vparser
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import dataflow
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import controlflow
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#import ast_code_generator # Python 2.7 does not support

‎pyverilog/ast_code_generator/__init__.py‎

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import sys
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if sys.version_info[0] < 3:
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import codegen

‎pyverilog/ast_code_generator/codegen.py‎

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# Copyright (C) 2013, Shinya Takamaeda-Yamazaki
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# License: Apache 2.0
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#-------------------------------------------------------------------------------
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from __future__ import absolute_import
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from __future__ import print_function
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import sys
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import os
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import math
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template = self.env.get_template(filename)
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template_dict = {
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'comp' : self.visit(node.comp),
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'caselist' : [ self.visit(case) for case in node.caselist ],
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'caselist' : [ self.indent(self.visit(case)) for case in node.caselist ],
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}
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rslt = template.render(template_dict)
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return rslt
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template = self.env.get_template(filename)
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template_dict = {
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'comp' : self.visit(node.comp),
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'caselist' : [ self.visit(case) for case in node.caselist ],
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'caselist' : [ self.indent(self.visit(case)) for case in node.caselist ],
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}
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rslt = template.render(template_dict)
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return rslt

‎pyverilog/ast_code_generator/sample/led.py‎

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from __future__ import absolute_import
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from __future__ import print_function
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import sys
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import os
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sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))) )

‎pyverilog/controlflow/__init__.py‎

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import sys
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if sys.version_info[0] < 3:
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import controlflow_analyzer
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import active_analyzer

‎pyverilog/controlflow/active_analyzer.py‎

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# License: Apache 2.0
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#-------------------------------------------------------------------------------
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from __future__ import absolute_import
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from __future__ import print_function
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import sys
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import os
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import pyverilog.utils.inference as inference
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import pyverilog.dataflow.reorder as reorder
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from pyverilog.dataflow.dataflow import *
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if sys.version_info[0] >= 3:
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import pyverilog.controlflow.splitter as splitter
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import pyverilog.controlflow.transition as transition
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from pyverilog.controlflow.controlflow_analyzer import VerilogControlflowAnalyzer
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else:
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import splitter
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import transition
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from controlflow_analyzer import VerilogControlflowAnalyzer
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import pyverilog.controlflow.splitter as splitter
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import pyverilog.controlflow.transition as transition
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from pyverilog.controlflow.controlflow_analyzer import VerilogControlflowAnalyzer
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class VerilogActiveConditionAnalyzer(VerilogControlflowAnalyzer):
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def __init__(self, topmodule, terms, binddict,

‎pyverilog/controlflow/active_range.py‎

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# License: Apache 2.0
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#-------------------------------------------------------------------------------
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from __future__ import absolute_import
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from __future__ import print_function
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import sys
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import os
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import pyverilog.utils.inference as inference
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import pyverilog.dataflow.reorder as reorder
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from pyverilog.dataflow.dataflow import *
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if sys.version_info[0] >= 3:
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import pyverilog.controlflow.splitter as splitter
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from pyverilog.controlflow.controlflow_analyzer import VerilogControlflowAnalyzer
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else:
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import splitter
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from controlflow_analyzer import VerilogControlflowAnalyzer
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import pyverilog.controlflow.splitter as splitter
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from pyverilog.controlflow.controlflow_analyzer import VerilogControlflowAnalyzer
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class VerilogActiveAnalyzer(VerilogControlflowAnalyzer):
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def __init__(self, topmodule, terms, binddict,

‎pyverilog/controlflow/controlflow_analyzer.py‎

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# License: Apache 2.0
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#-------------------------------------------------------------------------------
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from __future__ import absolute_import
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from __future__ import print_function
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import sys
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import os
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from pyverilog.dataflow.subset import VerilogSubset
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from pyverilog.dataflow.walker import VerilogDataflowWalker
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from pyverilog.dataflow.dataflow import *
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if sys.version_info[0] >= 3:
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import pyverilog.controlflow.splitter as splitter
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import pyverilog.controlflow.transition as transition
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else:
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import splitter
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import transition
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import pyverilog.controlflow.splitter as splitter
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import pyverilog.controlflow.transition as transition
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class VerilogControlflowAnalyzer(VerilogSubset):
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def __init__(self, topmodule, terms, binddict,

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