We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
1 parent b0b60e7 commit 4583b34Copy full SHA for 4583b34
README.md
@@ -7,7 +7,7 @@ Python-based Hardware Design Processing Toolkit for Verilog HDL
7
8
Copyright (C) 2013, Shinya Takamaeda-Yamazaki
9
10
-E-mail: shinya\_at\_is.naist.jp
+E-mail: takamaeda\_at\_ist.hokudai.ac.jp
11
12
13
License
0 commit comments