Example code in README is updated.

shtaxxx · shtaxxx · commit 43c9900773d1 · 2015-11-20T02:42:27.000+09:00
diff --git a/README.md b/README.md
@@ -342,21 +342,66 @@ Finally, let's try code generation. Please prepare a Python script as below. The
 A Verilog HDL code is represented by using the AST classes defined in 'vparser.ast'.
 
 ```python
+from __future__ import absolute_import
+from __future__ import print_function
+import sys
+import os
 import pyverilog.vparser.ast as vast
 from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
 
-params = vast.Paramlist(())
-clk = vast.Ioport( vast.Input('CLK') )
-rst = vast.Ioport( vast.Input('RST') )
-width = vast.Width( vast.IntConst('7'), vast.IntConst('0') )
-led = vast.Ioport( vast.Output('led', width=width) )
-ports = vast.Portlist( (clk, rst, led) )
-items = ( vast.Assign( vast.Identifier('led'), vast.IntConst('8') ) ,)
-ast = vast.ModuleDef("top", params, ports, items)
-
-codegen = ASTCodeGenerator()
-rslt = codegen.visit(ast)
-print(rslt)
+def main():
+    datawid = vast.Parameter( 'DATAWID', vast.Rvalue(vast.IntConst('32')) )
+    params = vast.Paramlist( [datawid] )
+    clk = vast.Ioport( vast.Input('CLK') )
+    rst = vast.Ioport( vast.Input('RST') )
+    width = vast.Width( vast.IntConst('7'), vast.IntConst('0') )
+    led = vast.Ioport( vast.Output('led', width=width) )
+    ports = vast.Portlist( [clk, rst, led] )
+
+    width = vast.Width( vast.Minus(vast.Identifier('DATAWID'), vast.IntConst('1')), vast.IntConst('0') )
+    count = vast.Reg('count', width=width)
+
+    assign = vast.Assign(
+        vast.Lvalue(vast.Identifier('led')), 
+        vast.Rvalue(
+            vast.Partselect(
+                vast.Identifier('count'), # count
+                vast.Minus(vast.Identifier('DATAWID'), vast.IntConst('1')), # [DATAWID-1:
+                vast.Minus(vast.Identifier('DATAWID'), vast.IntConst('8'))))) # :DATAWID-8]
+
+    sens = vast.Sens(vast.Identifier('CLK'), type='posedge')
+    senslist = vast.SensList([ sens ])
+
+    assign_count_true = vast.NonblockingSubstitution(
+        vast.Lvalue(vast.Identifier('count')),
+        vast.Rvalue(vast.IntConst('0')))
+    if0_true = vast.Block([ assign_count_true ])
+
+    # count + 1
+    count_plus_1 = vast.Plus(vast.Identifier('count'), vast.IntConst('1'))
+    assign_count_false = vast.NonblockingSubstitution(
+        vast.Lvalue(vast.Identifier('count')),
+        vast.Rvalue(count_plus_1))
+    if0_false = vast.Block([ assign_count_false ])
+
+    if0 = vast.IfStatement(vast.Identifier('RST'), if0_true, if0_false)
+    statement = vast.Block([ if0 ])
+
+    always = vast.Always(senslist, statement)
+
+    items = []
+    items.append(count)
+    items.append(assign)
+    items.append(always)
+
+    ast = vast.ModuleDef("top", params, ports, items)
+    
+    codegen = ASTCodeGenerator()
+    rslt = codegen.visit(ast)
+    print(rslt)
+
+if __name__ == '__main__':
+    main()
 ```
 
 Please type the command as below at the same directory with Pyverilog.
@@ -368,14 +413,27 @@ python test.py
 Then Verilog HDL code generated from the AST instances is displayed.
 
 ```verilog
-module top
+module top #
+(
+  parameter DATAWID = 32
+)
 (
   input CLK,
   input RST,
   output [7:0] led
 );
 
-  assign led = 8;
+  reg [DATAWID - 1:0] count;
+  assign led = count[DATAWID - 1:DATAWID - 8];
+
+  always @(posedge CLK) begin
+    if(RST) begin
+      count <= 0;
+    end else begin
+      count <= count + 1;
+    end
+  end
+
 
 endmodule
 ```
diff --git a/README.rst b/README.rst
@@ -377,21 +377,66 @@ using the AST classes defined in 'vparser.ast'.
 
 .. code:: python
 
+    from __future__ import absolute_import
+    from __future__ import print_function
+    import sys
+    import os
     import pyverilog.vparser.ast as vast
     from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
 
-    params = vast.Paramlist(())
-    clk = vast.Ioport( vast.Input('CLK') )
-    rst = vast.Ioport( vast.Input('RST') )
-    width = vast.Width( vast.IntConst('7'), vast.IntConst('0') )
-    led = vast.Ioport( vast.Output('led', width=width) )
-    ports = vast.Portlist( (clk, rst, led) )
-    items = ( vast.Assign( vast.Identifier('led'), vast.IntConst('8') ) ,)
-    ast = vast.ModuleDef("top", params, ports, items)
-
-    codegen = ASTCodeGenerator()
-    rslt = codegen.visit(ast)
-    print(rslt)
+    def main():
+        datawid = vast.Parameter( 'DATAWID', vast.Rvalue(vast.IntConst('32')) )
+        params = vast.Paramlist( [datawid] )
+        clk = vast.Ioport( vast.Input('CLK') )
+        rst = vast.Ioport( vast.Input('RST') )
+        width = vast.Width( vast.IntConst('7'), vast.IntConst('0') )
+        led = vast.Ioport( vast.Output('led', width=width) )
+        ports = vast.Portlist( [clk, rst, led] )
+
+        width = vast.Width( vast.Minus(vast.Identifier('DATAWID'), vast.IntConst('1')), vast.IntConst('0') )
+        count = vast.Reg('count', width=width)
+
+        assign = vast.Assign(
+            vast.Lvalue(vast.Identifier('led')), 
+            vast.Rvalue(
+                vast.Partselect(
+                    vast.Identifier('count'), # count
+                    vast.Minus(vast.Identifier('DATAWID'), vast.IntConst('1')), # [DATAWID-1:
+                    vast.Minus(vast.Identifier('DATAWID'), vast.IntConst('8'))))) # :DATAWID-8]
+
+        sens = vast.Sens(vast.Identifier('CLK'), type='posedge')
+        senslist = vast.SensList([ sens ])
+
+        assign_count_true = vast.NonblockingSubstitution(
+            vast.Lvalue(vast.Identifier('count')),
+            vast.Rvalue(vast.IntConst('0')))
+        if0_true = vast.Block([ assign_count_true ])
+
+        # count + 1
+        count_plus_1 = vast.Plus(vast.Identifier('count'), vast.IntConst('1'))
+        assign_count_false = vast.NonblockingSubstitution(
+            vast.Lvalue(vast.Identifier('count')),
+            vast.Rvalue(count_plus_1))
+        if0_false = vast.Block([ assign_count_false ])
+
+        if0 = vast.IfStatement(vast.Identifier('RST'), if0_true, if0_false)
+        statement = vast.Block([ if0 ])
+
+        always = vast.Always(senslist, statement)
+
+        items = []
+        items.append(count)
+        items.append(assign)
+        items.append(always)
+
+        ast = vast.ModuleDef("top", params, ports, items)
+        
+        codegen = ASTCodeGenerator()
+        rslt = codegen.visit(ast)
+        print(rslt)
+
+    if __name__ == '__main__':
+        main()
 
 Please type the command as below at the same directory with Pyverilog.
 
@@ -403,14 +448,27 @@ Then Verilog HDL code generated from the AST instances is displayed.
 
 .. code:: verilog
 
-    module top
+    module top #
+    (
+      parameter DATAWID = 32
+    )
     (
       input CLK,
       input RST,
       output [7:0] led
     );
 
-      assign led = 8;
+      reg [DATAWID - 1:0] count;
+      assign led = count[DATAWID - 1:DATAWID - 8];
+
+      always @(posedge CLK) begin
+        if(RST) begin
+          count <= 0;
+        end else begin
+          count <= count + 1;
+        end
+      end
+
 
     endmodule
 
diff --git a/examples/example_ast_code.py b/examples/example_ast_code.py
@@ -10,13 +10,50 @@
 from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
 
 def main():
-    params = vast.Paramlist(())
+    datawid = vast.Parameter( 'DATAWID', vast.Rvalue(vast.IntConst('32')) )
+    params = vast.Paramlist( [datawid] )
     clk = vast.Ioport( vast.Input('CLK') )
     rst = vast.Ioport( vast.Input('RST') )
     width = vast.Width( vast.IntConst('7'), vast.IntConst('0') )
     led = vast.Ioport( vast.Output('led', width=width) )
-    ports = vast.Portlist( (clk, rst, led) )
-    items = ( vast.Assign( vast.Identifier('led'), vast.IntConst('8') ) ,)
+    ports = vast.Portlist( [clk, rst, led] )
+
+    width = vast.Width( vast.Minus(vast.Identifier('DATAWID'), vast.IntConst('1')), vast.IntConst('0') )
+    count = vast.Reg('count', width=width)
+
+    assign = vast.Assign(
+        vast.Lvalue(vast.Identifier('led')), 
+        vast.Rvalue(
+            vast.Partselect(
+                vast.Identifier('count'), # count
+                vast.Minus(vast.Identifier('DATAWID'), vast.IntConst('1')), # [DATAWID-1:
+                vast.Minus(vast.Identifier('DATAWID'), vast.IntConst('8'))))) # :DATAWID-8]
+
+    sens = vast.Sens(vast.Identifier('CLK'), type='posedge')
+    senslist = vast.SensList([ sens ])
+
+    assign_count_true = vast.NonblockingSubstitution(
+        vast.Lvalue(vast.Identifier('count')),
+        vast.Rvalue(vast.IntConst('0')))
+    if0_true = vast.Block([ assign_count_true ])
+
+    # count + 1
+    count_plus_1 = vast.Plus(vast.Identifier('count'), vast.IntConst('1'))
+    assign_count_false = vast.NonblockingSubstitution(
+        vast.Lvalue(vast.Identifier('count')),
+        vast.Rvalue(count_plus_1))
+    if0_false = vast.Block([ assign_count_false ])
+
+    if0 = vast.IfStatement(vast.Identifier('RST'), if0_true, if0_false)
+    statement = vast.Block([ if0 ])
+
+    always = vast.Always(senslist, statement)
+
+    items = []
+    items.append(count)
+    items.append(assign)
+    items.append(always)
+
     ast = vast.ModuleDef("top", params, ports, items)
     
     codegen = ASTCodeGenerator()
diff --git a/tests/ast_code_generator_test/test_ast_assign.py b/tests/ast_code_generator_test/test_ast_assign.py
@@ -19,13 +19,14 @@
 """
 
 def test():
-    params = vast.Paramlist(())
+    params = vast.Paramlist( [] )
     clk = vast.Ioport( vast.Input('CLK') )
     rst = vast.Ioport( vast.Input('RST') )
     width = vast.Width( vast.IntConst('7'), vast.IntConst('0') )
     led = vast.Ioport( vast.Output('led', width=width) )
     ports = vast.Portlist( (clk, rst, led) )
-    items = ( vast.Assign( vast.Identifier('led'), vast.IntConst('8') ) ,)
+    items = [ vast.Assign( vast.Lvalue(vast.Identifier('led')),
+                           vast.Rvalue(vast.IntConst('8'))) ]
     ast = vast.ModuleDef("top", params, ports, items)
     
     codegen = ASTCodeGenerator()
