VERSION as TEXT

Author: shtaxxx

MANIFEST.in

@@ -3,6 +3,8 @@ include LICENSE
 include pytest.ini
 include .travis.yml
 include Makefile
+include pyverilog/Makefile
+include pyverilog/VERSION
 recursive-include tests *
 recursive-include examples *
 recursive-include verilogcode *

pyverilog/VERSION

@@ -0,0 +1 @@
+1.2.0

pyverilog/__init__.py

@@ -1 +1,6 @@
-__version__ = "1.2.0"
+from __future__ import absolute_import
+from __future__ import print_function
+
+import os
+
+__version__ = open(os.path.join(os.path.dirname(__file__), "VERSION")).read().splitlines()[0]

setup.py

@@ -2,15 +2,15 @@
 
 import re
 import os
-import pyverilog
 
 
 def read(filename):
-    return open(os.path.join(os.path.dirname(__file__), filename), encoding='utf8').read()
+    # return open(os.path.join(os.path.dirname(__file__), filename), encoding='utf8').read()
+    return open(os.path.join(os.path.dirname(__file__), filename)).read()
 
 
 setup(name='pyverilog',
-      version=pyverilog.__version__,
+      version=read('pyverilog/VERSION'),
       description='Python-based Hardware Design Processing Toolkit for Verilog HDL: Parser, Dataflow Analyzer, Controlflow Analyzer and Code Generator',
       long_description=read('README.md'),
       long_description_content_type="text/markdown",
@@ -19,7 +19,8 @@ def read(filename):
       license="Apache License 2.0",
       url='https://github.com/PyHDI/Pyverilog',
       packages=find_packages(),
-      package_data={'pyverilog.ast_code_generator': ['template/*'], },
+      package_data={'pyverilog': ['VERSION'],
+                    'pyverilog.ast_code_generator': ['template/*'], },
       install_requires=['Jinja2>=2.10'],
       extras_require={
           'test': ['pytest>=3.8.1', 'pytest-pythonpath>=0.7.3'],