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‎README.md‎

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@@ -464,7 +464,10 @@ Related Project and Site
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==============================
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[Veriloggen](https://github.com/PyHDI/veriloggen)
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- A library for constructing a Verilog HDL source code in Python
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- A Mixed-Paradigm Hardware Construction Framework
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[NNgen](https://github.com/NNgen/nngen)
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- A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network
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[IPgen](https://github.com/PyHDI/ipgen)
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- IP-core package generator for AXI4/Avalon

‎README.rst‎

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@@ -493,8 +493,11 @@ Then Verilog HDL code generated from the AST instances is displayed.
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Related Project and Site
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========================
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`Veriloggen <https://github.com/PyHDI/veriloggen>`__ - A library for
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constructing a Verilog HDL source code in Python
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`Veriloggen <https://github.com/PyHDI/veriloggen>`__ - A Mixed-Paradigm
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Hardware Construction Framework
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`NNgen <https://github.com/NNgen/nngen>`__ - A Fully-Customizable
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Hardware Synthesis Compiler for Deep Neural Network
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`IPgen <https://github.com/PyHDI/ipgen>`__ - IP-core package generator
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for AXI4/Avalon

‎pyverilog/ast_code_generator/codegen.py‎

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@@ -258,6 +258,7 @@ def visit_Variable(self, node):
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'name': escape(node.name),
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'width': '' if node.width is None else self.visit(node.width),
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'signed': node.signed,
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'dimensions': '' if node.dimensions is None else self.visit(node.dimensions),
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}
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rslt = template.render(template_dict)
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return rslt
@@ -269,6 +270,7 @@ def visit_Input(self, node):
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'name': escape(node.name),
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'width': '' if node.width is None else self.visit(node.width),
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'signed': node.signed,
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'dimensions': '' if node.dimensions is None else self.visit(node.dimensions),
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}
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rslt = template.render(template_dict)
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return rslt
@@ -280,6 +282,7 @@ def visit_Output(self, node):
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'name': escape(node.name),
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'width': '' if node.width is None else self.visit(node.width),
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'signed': node.signed,
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'dimensions': '' if node.dimensions is None else self.visit(node.dimensions),
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}
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rslt = template.render(template_dict)
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return rslt
@@ -291,6 +294,7 @@ def visit_Inout(self, node):
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'name': escape(node.name),
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'width': '' if node.width is None else self.visit(node.width),
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'signed': node.signed,
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'dimensions': '' if node.dimensions is None else self.visit(node.dimensions),
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}
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rslt = template.render(template_dict)
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return rslt
@@ -302,6 +306,7 @@ def visit_Tri(self, node):
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'name': escape(node.name),
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'width': '' if node.width is None else self.visit(node.width),
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'signed': node.signed,
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'dimensions': '' if node.dimensions is None else self.visit(node.dimensions),
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}
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rslt = template.render(template_dict)
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return rslt
@@ -313,6 +318,7 @@ def visit_Wire(self, node):
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'name': escape(node.name),
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'width': '' if node.width is None else self.visit(node.width),
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'signed': node.signed,
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'dimensions': '' if node.dimensions is None else self.visit(node.dimensions),
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}
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rslt = template.render(template_dict)
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return rslt
@@ -324,30 +330,7 @@ def visit_Reg(self, node):
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'name': escape(node.name),
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'width': '' if node.width is None else self.visit(node.width),
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'signed': node.signed,
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}
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rslt = template.render(template_dict)
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return rslt
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def visit_WireArray(self, node):
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filename = getfilename(node)
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template = self.get_template(filename)
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template_dict = {
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'name': escape(node.name),
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'width': '' if node.width is None else self.visit(node.width),
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'length': self.visit(node.length),
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'signed': node.signed,
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}
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rslt = template.render(template_dict)
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return rslt
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def visit_RegArray(self, node):
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filename = getfilename(node)
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template = self.get_template(filename)
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template_dict = {
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'name': escape(node.name),
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'width': '' if node.width is None else self.visit(node.width),
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'length': self.visit(node.length),
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'signed': node.signed,
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'dimensions': '' if node.dimensions is None else self.visit(node.dimensions),
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}
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rslt = template.render(template_dict)
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return rslt
@@ -388,7 +371,8 @@ def visit_Ioport(self, node):
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'second': '' if node.second is None else node.second.__class__.__name__.lower(),
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'name': escape(node.first.name),
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'width': '' if node.first.width is None else self.visit(node.first.width),
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'signed': node.first.signed or (node.second is not None and node.second.signed)
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'signed': node.first.signed or (node.second is not None and node.second.signed),
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'dimensions': '' if node.first.dimensions is None else self.visit(node.first.dimensions)
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}
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rslt = template.render(template_dict)
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return rslt

‎pyverilog/ast_code_generator/list_ast.txt‎

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@@ -6,6 +6,7 @@ Portlist
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Port
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Width
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Length
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Dimensions
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Identifier
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Value
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Constant
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Tri
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Wire
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Reg
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WireArray
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RegArray
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Integer
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Real
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Genvar

‎pyverilog/ast_code_generator/template/inout.txt‎

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@@ -1 +1 @@
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inout {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }};
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inout {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }}{% if dimensions != '' %} {{ dimensions }}{% endif %};

‎pyverilog/ast_code_generator/template/input.txt‎

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@@ -1 +1 @@
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input {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }};
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input {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }}{% if dimensions != '' %} {{ dimensions }}{% endif %};

‎pyverilog/ast_code_generator/template/ioport.txt‎

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@@ -1 +1 @@
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{{ first }} {% if second != '' %}{{ second }} {% endif %}{% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }}
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{{ first }} {% if second != '' %}{{ second }} {% endif %}{% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }}{% if dimensions != '' %} {{ dimensions }}{% endif %}

‎pyverilog/ast_code_generator/template/output.txt‎

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@@ -1 +1 @@
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output {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }};
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output {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }}{% if dimensions != '' %} {{ dimensions }}{% endif %};

‎pyverilog/ast_code_generator/template/reg.txt‎

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@@ -1 +1 @@
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reg {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }};
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reg {% if signed %}signed {% endif %}{% if width != '' %}{{ width }} {% endif %}{{ name }}{% if dimensions != '' %} {{ dimensions }}{% endif %};

‎pyverilog/ast_code_generator/template/regarray.txt‎

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