Merge pull request #49 from tomchean/master

add Sla operator support and fix operator percedence according to latest IEEE verilog document

Author: shtaxxx

pyverilog/ast_code_generator/template/sla.txt

@@ -0,0 +1 @@
+({{ left }} {{ op }} {{ right }})

pyverilog/utils/op2mark.py

@@ -12,7 +12,7 @@
     'Uor':'|', 'Unor':'~|', 'Uxor':'^', 'Uxnor':'~^',
     'Power':'**', 'Times':'*', 'Divide':'/', 'Mod':'%', 
     'Plus':'+', 'Minus':'-',
-    'Sll':'<<', 'Srl':'>>', 'Sra':'>>>',
+    'Sll':'<<', 'Srl':'>>', 'Sla':'<<<', 'Sra':'>>>',
     'LessThan':'<', 'GreaterThan':'>', 'LessEq':'<=', 'GreaterEq':'>=',
     'Eq':'==', 'NotEq':'!=', 'Eql':'===', 'NotEql':'!==',
     'And':'&', 'Xor':'^', 'Xnor':'~^',
@@ -30,13 +30,14 @@ def op2mark(op):
     'Power':1,
     'Times':2, 'Divide':2, 'Mod':2, 
     'Plus':3, 'Minus':3,
-    'Sll':4, 'Srl':4, 'Sra':4,
+    'Sll':4, 'Srl':4, 'Sla':4, 'Sra':4,
     'LessThan':5, 'GreaterThan':5, 'LessEq':5, 'GreaterEq':5,
     'Eq':6, 'NotEq':6, 'Eql':6, 'NotEql':6,
-    'And':7, 'Xor':7, 'Xnor':7,
-    'Or':8,
-    'Land':9,
-    'Lor':10
+    'And':7,
+    'Xor':8, 'Xnor':8,
+    'Or':9,
+    'Land':10,
+    'Lor':11
     }
 
 def op2order(op):

pyverilog/vparser/ast.py

@@ -585,7 +585,9 @@ class Sll(Operator):
 class Srl(Operator):
     pass
 
-
+class Sla(Operator):
+    pass
+        
 class Sra(Operator):
     pass
 

pyverilog/vparser/parser.py

@@ -37,7 +37,8 @@ class VerilogParser(PLYParser):
         ('left', 'LOR'),
         ('left', 'LAND'),
         ('left', 'OR'),
-        ('left', 'AND', 'XOR', 'XNOR'),
+        ('left', 'XOR', 'XNOR'),
+        ('left', 'AND'),
         ('left', 'EQ', 'NE', 'EQL', 'NEL'),
         ('left', 'LT', 'GT', 'LE', 'GE'),
         ('left', 'LSHIFT', 'RSHIFT', 'LSHIFTA', 'RSHIFTA'),
@@ -1030,7 +1031,7 @@ def p_expression_srl(self, p):
 
     def p_expression_sla(self, p):
         'expression : expression LSHIFTA expression'
-        p[0] = Sll(p[1], p[3], lineno=p.lineno(1))
+        p[0] = Sla(p[1], p[3], lineno=p.lineno(1))
         p.set_lineno(0, p.lineno(1))
 
     def p_expression_sra(self, p):