README

shtaxxx · shtaxxx · commit 30457a2bfd55 · 2015-11-23T15:33:02.000+09:00
diff --git a/MANIFEST.in b/MANIFEST.in
@@ -1,5 +1,8 @@
 include README.md
 include README.rst
+include LICENSE.txt
+include pytest.ini
+include .travis.yml
 include Makefile
 recursive-include tests *
 recursive-include examples *
diff --git a/README.md b/README.md
@@ -1,6 +1,8 @@
 Pyverilog
 ==============================
 
+[![Build Status](https://travis-ci.org/PyHDI/Pyverilog.svg)](https://travis-ci.org/PyHDI/Pyverilog)
+
 Python-based Hardware Design Processing Toolkit for Verilog HDL
 
 Copyright (C) 2013, Shinya Takamaeda-Yamazaki
diff --git a/README.rst b/README.rst
@@ -1,6 +1,8 @@
 Pyverilog
 =========
 
+|Build Status|
+
 Python-based Hardware Design Processing Toolkit for Verilog HDL
 
 Copyright (C) 2013, Shinya Takamaeda-Yamazaki
@@ -482,3 +484,6 @@ Thanks for your contribution!
 
 `shtaxxx.hatenablog.com <http://shtaxxx.hatenablog.com/entry/2014/01/01/045856>`__
 - Blog entry for introduction and examples of Pyverilog (in Japansese)
+
+.. |Build Status| image:: https://travis-ci.org/PyHDI/Pyverilog.svg
+   :target: https://travis-ci.org/PyHDI/Pyverilog
