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1 parent acb8e87 commit 9d64417Copy full SHA for 9d64417
CMakeLists.txt
@@ -38,15 +38,15 @@ ADD_FLEX_BISON_DEPENDENCY(verilog_lexer verilog_parser)
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# Set the output folder to example
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set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${PROJECT_SOURCE_DIR}/example)
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+# A sample parser
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add_executable(sample_parser
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${PROJECT_SOURCE_DIR}/example/sample_parser.cpp
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${FLEX_verilog_lexer_OUTPUTS}
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${BISON_verilog_parser_OUTPUTS}
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)
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target_link_libraries(sample_parser stdc++fs)
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-
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+# A drop-in replacement OpenTimer Verilog parser
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add_executable(ot_parser
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${PROJECT_SOURCE_DIR}/example/ot_parser.cpp
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