Update README.md

Author: OpenRealTimeSimulation

README.md

@@ -8,11 +8,11 @@ Code generation tools for creation of CPU or FPGA real-time simulation C++ solve
 
 These tools are part of the Open Real-Time Simulation (ORTiS) framework.
 
-Utilizing solvers generated by these tools along with FPGA High-Level Synthesis (HLS) and execution, real-time simulation of sizable power electronic systems with high frequency dynamics at 35 nanosecond time steps are achievable.
+Utilizing solvers generated by these tools along with FPGA High-Level Synthesis (HLS) and execution, real-time simulation of sizable power electronic systems with high frequency dynamics at 35 or less nanosecond time steps are achievable.
 
 Solvers generated by the tools utilize the Latency Based Linear Multi-step Compound (LB-LMC) simulation method to solve system models.  
 
-Solvers are generated custom-tailored for a given system model which can be defined in plain-text netlists.  User defined components in the systems are supported through C++ extensions to the codegen tool library.  Multi-FPGA solver creation for decomposed systems is supported.
+Solvers are generated as custom-tailored C++ code for a given system model defined in plain-text netlists.  User defined components in the systems are supported through C++ extensions to the codegen tool library.  Multi-FPGA solver creation for decomposed systems is supported.
 
 The tools include the LB-LMC C++ Solver Code Generation C++ Library along with a Command Line Interface (CLI) tool to allow creation of simulation solvers via either C++ programming or command shell environments.
 
@@ -27,7 +27,7 @@ http://eigen.tuxfamily.org/
 
 Solvers generated by the tools are C++03 complaint and do not have any dependencies.
 
-High Level Synthesis (HLS) of C++ solvers for FPGA execution is supported using Xilinx Vivado HLx suite for Xilinx FPGA devices.  Solver FPGA cores created with HLS can be utilized on National Instruments FPGA-based platforms, Xilinx FPGA evaluation kits, and other platforms that incorporate Xilinx FPGAs.
+High Level Synthesis (HLS) of C++ solvers into Register Transfer Level (RTL) designs for FPGA execution is supported using Xilinx Vivado HLx suite for Xilinx FPGA devices.  Solver FPGA cores created with HLS can be utilized on National Instruments FPGA-based platforms, Xilinx FPGA evaluation kits, and other platforms that incorporate Xilinx FPGAs.
 
 ## License
 
@@ -47,7 +47,11 @@ url: https://ieeexplore.ieee.org/document/8847940
 
 **The code generation tools have been applied in the following recent work:**
 
-* M. Vygoder, M. Milton, J. Gudex, R. Cuzner, and A. Benigni, ``A Hardware-in-the-Loop Platform for DC Protection,'' IEEE Journal of Emerging and Selected Topics in Power Electronics, Aug. 2020, Early Access.
+* M. Difronzo, Md. M. Biswas, M. Milton, H. Ginn III, and A. Benigni, ``System Level Real-Time Simulation and Hardware-in-the-Loop Testing of MMCs,'' Energies, vol. 14, no. 11, May 2021.
+doi:  10.3390/en14113046 
+url: https://www.mdpi.com/1996-1073/14/11/3046
+
+* M. Vygoder, M. Milton, J. Gudex, R. Cuzner, and A. Benigni, ``A Hardware-in-the-Loop Platform for DC Protection,'' IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 9, no.3, pp. 2605-2619, June 2021.
 doi:  10.1109/JESTPE.2020.3017769
 url: https://ieeexplore.ieee.org/document/9171341