testing load hazard

Author: wig-nesh

pipelined/modules/data_memory.hex

@@ -1,5 +1,5 @@
 // 0x00000000
-00
+05
 00
 00
 00

pipelined/testcases/8.s

@@ -0,0 +1,8 @@
+begin:
+    ld x2, 0(x0)
+    addi x4, x2, 1
+    add x8, x6, x2
+    add x9, x4, x2
+
+end:
+    nop

pipelined/verilog/testbench_pipelined.v

@@ -16,13 +16,8 @@ module testbench_pipelined();
         reset = 1;
 
         // Initialize instruction memory first
-        cpu.imem.memory[0] = 32'b00000000001100000000000010010011;
-        cpu.imem.memory[1] = 32'b00000000011100000000000100010011;
-        cpu.imem.memory[2] = 32'b00000000000000001000100001100011;
-        cpu.imem.memory[3] = 32'b00000000000100010000000100110011;
-        cpu.imem.memory[4] = 32'b11111111111100001000000010010011;
-        cpu.imem.memory[5] = 32'b11111110000000000000101011100011;
-        cpu.imem.memory[6] = 32'b00000000000000000000000000000000;
+        cpu.imem.memory[0] = 32'b00000000000000000010000100000011;
+        cpu.imem.memory[1] = 32'b00000000000000000000000000000000;
 
         // promper initialization
         #10 reset = 0;