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Seq, Pipe Both support, Index Changed
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-14631
lines changed

4 files changed

+524
-14631
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demo/index.html

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -377,4 +377,4 @@ <h4>GitHub Repository</h4>
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</footer>
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</div>
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</body>
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</html>
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</html>

pipelined/visualization/index.html

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -10,19 +10,19 @@
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<body>
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<div class="container">
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<div class="header">
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<h1>Pipelined CPU Simulator</h1>
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</div>
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<div class="controls">
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<button id="prev">Previous</button>
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<button id="play-pause">Play</button>
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<button id="next">Next</button>
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<select id="speed">
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<option value="1000">1x</option>
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<option value="500">2x</option>
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<option value="200">5x</option>
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</select>
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<span id="cycle-display">Cycle: 1</span>
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<h1>RISC-V CPU Visualizer</h1>
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<div class="controls">
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<button id="prev" disabled>Previous Cycle</button>
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<span id="cycle-display">Cycle: 0</span>
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<button id="next">Next Cycle</button>
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<button id="play-pause">Play</button>
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<select id="speed">
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<option value="1000">1x Speed</option>
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<option value="200">5x Speed</option>
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<option value="100">10x Speed</option>
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<option value="20">50x Speed</option>
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</select>
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</div>
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</div>
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<div class="main-view">

sequential/verilog/testbench_sequential.v

Lines changed: 31 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -26,18 +26,37 @@ module testbench_sequential();
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);
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initial begin
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cpu.imem.memory[0] = 32'b00000000010100000000000010010011;
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cpu.imem.memory[1] = 32'b00000000001000000000000100010011;
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cpu.imem.memory[2] = 32'b00000000000000000000000110110011;
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cpu.imem.memory[3] = 32'b00000010000000001000000001100011;
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cpu.imem.memory[4] = 32'b00000000000000010000001000010011;
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cpu.imem.memory[5] = 32'b00000000000000100000100001100011;
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cpu.imem.memory[6] = 32'b00000000000100011000000110110011;
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cpu.imem.memory[7] = 32'b11111111111100100000001000010011;
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cpu.imem.memory[8] = 32'b11111110000000000000101011100011;
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cpu.imem.memory[9] = 32'b11111111111100001000000010010011;
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cpu.imem.memory[10] = 32'b11111110000000000000001011100011;
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cpu.imem.memory[11] = 32'b00000000000000000000000000000000;
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cpu.imem.memory[0] = 32'b00000000111100000000000010010011;
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cpu.imem.memory[1] = 32'b00000001100100000000000100010011;
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cpu.imem.memory[2] = 32'b00000000011100000000000110010011;
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cpu.imem.memory[3] = 32'b00000001001000000000001000010011;
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cpu.imem.memory[4] = 32'b00000000001000001000001010110011;
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cpu.imem.memory[5] = 32'b01000000000100010000001100110011;
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cpu.imem.memory[6] = 32'b00000000001100001111001110110011;
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cpu.imem.memory[7] = 32'b00000000001100001110010000110011;
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cpu.imem.memory[8] = 32'b00000000010100000010000000100011;
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cpu.imem.memory[9] = 32'b00000000011000000010010000100011;
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cpu.imem.memory[10] = 32'b00000000000000000010010010000011;
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cpu.imem.memory[11] = 32'b00000000100000000010010100000011;
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cpu.imem.memory[12] = 32'b00000000101001001000010110110011;
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cpu.imem.memory[13] = 32'b01000000101001001000011000110011;
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cpu.imem.memory[14] = 32'b00000000110001011000110001100011;
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cpu.imem.memory[15] = 32'b00000110010000000000011010010011;
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cpu.imem.memory[16] = 32'b00000000110001011110011100110011;
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cpu.imem.memory[17] = 32'b00000000110001011111011110110011;
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cpu.imem.memory[18] = 32'b00000000111000000010100000100011;
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cpu.imem.memory[19] = 32'b00000000111100000010110000100011;
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cpu.imem.memory[20] = 32'b00000011001000000000100000010011;
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cpu.imem.memory[21] = 32'b00000000111110000000100010110011;
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cpu.imem.memory[22] = 32'b01000000111010001000100100110011;
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cpu.imem.memory[23] = 32'b00000001001010001000111001100011;
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cpu.imem.memory[24] = 32'b00000001000000000010100110000011;
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cpu.imem.memory[25] = 32'b00000001100000000010101000000011;
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cpu.imem.memory[26] = 32'b00000001010010011110101010110011;
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cpu.imem.memory[27] = 32'b00000001010010011111101100110011;
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cpu.imem.memory[28] = 32'b00000011010100000010000000100011;
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cpu.imem.memory[29] = 32'b00000011011000000010010000100011;
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cpu.imem.memory[30] = 32'b00000000000000000000000000000000;
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end
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