Report Added

Author: MostlyKIGuess

README.md

@@ -19,10 +19,36 @@ PS: I recommend testing 2.s ( a really long programme that checks all the ALU fu
 ./test_sequential.sh 6.s
 ```
 
+## Pipelined Implementation
+
+The pipelined implementation features a 5-stage pipeline with hazard detection, data forwarding, and branch prediction. To run tests on the pipelined CPU:
+
+
+```sh
+cd pipelined
+chmod +x test_pipelined.sh
+./test_pipelined.sh <filename>.s
+```
+
+### Key Pipelined Features:
+
+- 5-stage pipeline: IF, ID, EX, MEM, and WB stages
+- Static branch prediction: Always-taken strategy for branches
+- Data hazard handling: Forwarding paths for most hazards, stalling for load-use hazards
+- Control hazard handling: Pipeline flush on branch misprediction
+- Performance: Multiple test cases demonstrate improved throughput over sequential design
+
+
+### Test Cases:
+- 2.s: Tests loop with data dependencies, showcasing forwarding paths
+- 4.s: Tests branch prediction with unconditional branches
+- 7.s: Tests branch prediction and control hazard handling
+- 8.s: Tests load-use hazard detection and stalling mechanism
+
 ## Assembly Instructions Supported
 
 The assembler supports a subset of RISC-V instructions:
-- **R-type**: `add`, `sub`, `or`, `and`
+- **R-type**: `add`, `sub`, `or`, `and`, `addi`
 - **I-type**: `addi`, `ld` (load doubleword)
 - **S-type**: `sd` (store doubleword)
 - **B-type**: `beq` (branch if equal)

pipelined/verilog/testbench_pipelined.v

@@ -16,11 +16,13 @@ module testbench_pipelined();
         reset = 1;
 
         // Initialize instruction memory first
-        cpu.imem.memory[0] = 32'b00000000000000000010000100000011;
-        cpu.imem.memory[1] = 32'b00000000000100010000001000010011;
-        cpu.imem.memory[2] = 32'b00000000001000110000010000110011;
-        cpu.imem.memory[3] = 32'b00000000001000100000010010110011;
-        cpu.imem.memory[4] = 32'b00000000000000000000000000000000;
+        cpu.imem.memory[0] = 32'b00000000001100000000000010010011;
+        cpu.imem.memory[1] = 32'b00000000011100000000000100010011;
+        cpu.imem.memory[2] = 32'b00000000000000001000100001100011;
+        cpu.imem.memory[3] = 32'b00000000000100010000000100110011;
+        cpu.imem.memory[4] = 32'b11111111111100001000000010010011;
+        cpu.imem.memory[5] = 32'b11111110000000000000101011100011;
+        cpu.imem.memory[6] = 32'b00000000000000000000000000000000;
 
         // promper initialization
         #10 reset = 0;