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fibonaci on demo with updated memorh
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‎demo/index.html‎

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<head>
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<meta charset="UTF-8" />
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<meta name="viewport" content="width=device-width, initial-scale=1.0" />
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<meta name="description" content="Interactive visualization of RISC-V CPU implementations, including sequential and pipelined architectures." />
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<meta name="keywords" content="RISC-V, CPU, Visualization, Sequential, Pipelined, Processor, Simulation" />
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<meta
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name="description"
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content="Interactive visualization of RISC-V CPU implementations, including sequential and pipelined architectures."
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/>
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<meta
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name="keywords"
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content="RISC-V, CPU, Visualization, Sequential, Pipelined, Processor, Simulation"
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/>
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<meta name="author" content="MostlyKIGuess" />
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<link href="https://fonts.googleapis.com/icon?family=Material+Icons" rel="stylesheet">
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<link
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href="https://fonts.googleapis.com/icon?family=Material+Icons"
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rel="stylesheet"
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/>
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<title>RISC-V CPU Visualizer</title>
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<link rel="icon" type="image/jpg" href="./catprocessor.jpg" />
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<link rel="stylesheet" href="css/styles.css" />
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<div class="container">
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<div class="header-container">
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<h1>RISC-V CPU Visualization</h1>
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<div class="top-links">
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<a href="https://github.com/MostlyKIGuess/RISC-V-Processor-Implementation/" class="github-link" target="_blank">
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<a
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href="https://github.com/MostlyKIGuess/RISC-V-Processor-Implementation/"
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class="github-link"
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target="_blank"
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>
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<span class="icon">&#xe043;</span> GitHub Repository
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</a>
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<a href="./report/Report.pdf" class="report-link" download>
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</ul>
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<div class="button-container">
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<a href="sequential/index.html" class="button">Launch Sequential CPU</a>
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<a href="sequential/index.html" class="button"
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>Launch Sequential CPU</a
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>
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</div>
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</div>
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</ul>
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<div class="button-container">
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<a href="pipelined/index.html" class="button">Launch Pipelined CPU</a>
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<a href="pipelined/index.html" class="button"
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>Launch Pipelined CPU</a
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>
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</div>
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</div>
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</div>
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<div class="program-container">
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<h3>Sequential CPU Program</h3>
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<p>
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The Sequential CPU demo executes the following RISC-V program:
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</p>
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<p>The Sequential CPU demo executes the following RISC-V program:</p>
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<div class="demo-code">
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<pre><code>addi x1, x0, 15 # Initialize x1 = 15
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addi x2, x0, 25 # Initialize x2 = 25
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</p>
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<ol>
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<li>
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<strong>Register Initialization</strong>: Sets initial values
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in registers x1-x4 using immediate values
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<strong>Register Initialization</strong>: Sets initial values in
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registers x1-x4 using immediate values
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</li>
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<li>
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<strong>Arithmetic Operations</strong>: Performs addition and
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subtraction between registers
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</li>
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<li>
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<strong>Logical Operations</strong>: Performs bitwise AND and
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OR operations
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<strong>Logical Operations</strong>: Performs bitwise AND and OR
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operations
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</li>
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<li>
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<strong>Memory Operations</strong>: Stores and loads values
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to/from memory
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</li>
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<li>
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<strong>Branching</strong>: Uses conditional branches to
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control program flow
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<strong>Branching</strong>: Uses conditional branches to control
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program flow
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</li>
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<li>
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<strong>Control Flow</strong>: Demonstrates label-based
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<h3>Pipelined CPU Program</h3>
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<p>The Pipelined CPU demo executes the following RISC-V program:</p>
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<div class="demo-code">
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<pre><code>begin:
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addi x1, x0, 3 # x1 = 3
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addi x2, x0, 7 # x2 = 7
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loop:
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beq x1, x0, exit # if x1==0, end program
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add x2, x2, x1 # x2 = x1 + x2
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addi x1, x1, -1 # x1--
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beq x0, x0, loop # loop
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exit:
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nop # No operation</code></pre>
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<pre><code>start:
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ld x1, 0(x0) # Load n from memory
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addi x2, x0, 0 # x2 = 0 (Fib(0))
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addi x3, x0, 1 # x3 = 1 (Fib(1))
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beq x1, x0, done # If n == 0, return Fib(0)
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addi x1, x1, -1 # Decrement n by 1 to account for Fib(1)
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beq x1, x0, done1 # If n == 1, return Fib(1)
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loop:
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add x4, x2, x3 # x4 = x2 + x3 (Fib(n) = Fib(n-1) + Fib(n-2))
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add x2, x3, x0 # x2 = x3 (shift Fib(n-1) to Fib(n-2))
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add x3, x4, x0 # x3 = x4 (shift Fib(n) to Fib(n-1))
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addi x1, x1, -1 # Decrement n
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beq x1, x0, done1 # Repeat until n == 0
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beq x0, x0, loop
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done1:
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add x4, x3, x0 # Return Fib(1)
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done:
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# x4 holds the Fibonacci result
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addi x0, x0, 0
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nop</code></pre>
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</div>
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<div class="program-explanation">
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<h4>Program Explanation:</h4>
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<p>
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This program is specifically designed to demonstrate pipeline
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hazards and their resolution:
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This Fibonacci calculator demonstrates pipeline hazards and their
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resolution:
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</p>
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<ol>
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<li>
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<strong>Data Hazards</strong>: The program creates register
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dependencies between instructions (x1 and x2 are both read and
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written in consecutive instructions), triggering the
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forwarding unit.
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dependencies between instructions (registers are both read and
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written in consecutive instructions), triggering the forwarding
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unit.
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</li>
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<li>
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<strong>Control Hazards</strong>: The branch instructions
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create control hazards that demonstrate branch prediction and
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pipeline flushing.
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<strong>Control Hazards</strong>: The multiple branch
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instructions create control hazards that demonstrate branch
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prediction and pipeline flushing.
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</li>
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<li>
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<strong>Loop Implementation</strong>: The program implements a
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simple counting loop that:
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<strong>Fibonacci Implementation</strong>: The program
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calculates the Fibonacci sequence:
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<ul>
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<li>Starts with x1 = 3 and x2 = 7</li>
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<li>
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Adds the current value of x1 to x2 on each iteration
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</li>
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<li>Decrements x1 by 1 on each iteration</li>
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<li>Exits when x1 reaches 0</li>
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<li>Loads n=10 from memory location 0</li>
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<li>Initializes with Fib(0)=0 and Fib(1)=1</li>
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<li>Iteratively computes Fib(n) = Fib(n-1) + Fib(n-2)</li>
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<li>For n=10, the result will be Fib(10)=55</li>
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</ul>
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</li>
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</ol>
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<p>
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When the program completes, x1 will be 0 and x2 will be 7+3+2+1
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= 13. By following the execution, you can observe how the
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pipeline handles data and control hazards in real-time.
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When the program completes, x4 will contain the 10th Fibonacci
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number (55). Following the execution shows how the pipeline
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handles data dependencies and branch predictions in this more
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complex algorithm. The first instruction demonstrates memory
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access hazards by loading the value from memory.
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</p>
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</div>
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</div>
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</li>
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</ul>
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</div>
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<div id="resources" class="resources">
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<h2>Additional Resources</h2>
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<div class="resource-links">
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<p>Detailed documentation of the RISC-V implementation</p>
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</div>
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</a>
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<a href="https://github.com/MostlyKIGuess/RISC-V-Processor-Implementation/" class="resource-btn" target="_blank">
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<a
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href="https://github.com/MostlyKIGuess/RISC-V-Processor-Implementation/"
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class="resource-btn"
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target="_blank"
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>
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<span class="icon">&#xe043;</span>
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<div class="resource-info">
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<h4>GitHub Repository</h4>
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</a>
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</div>
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</div>
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<footer>
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<p>RISC-V CPU Visualizer</p>
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<p>Made with <span class="icon">&#xe87d;</span></p>
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<p>&copy; 2025 All rights reserved.</p>
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</footer>
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</div>
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</body>
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</html>

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