@@ -186,5 +186,104 @@ SystemClock_Config(void) {
186186 Error_Handler ();
187187 }
188188}
189+ #elif defined(STM32N6xx )
190+ void
191+ SystemClock_Config (void ) {
192+ RCC_OscInitTypeDef RCC_OscInitStruct = {0 };
193+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0 };
194+
195+ /** Configure the System Power Supply
196+ */
197+ if (HAL_PWREx_ConfigSupply (PWR_EXTERNAL_SOURCE_SUPPLY ) != HAL_OK ) {
198+ Error_Handler ();
199+ }
200+
201+ /* Enable HSI */
202+ RCC_OscInitStruct .OscillatorType = RCC_OSCILLATORTYPE_HSI ;
203+ RCC_OscInitStruct .HSIState = RCC_HSI_ON ;
204+ RCC_OscInitStruct .HSIDiv = RCC_HSI_DIV1 ;
205+ RCC_OscInitStruct .HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT ;
206+ RCC_OscInitStruct .PLL1 .PLLState = RCC_PLL_NONE ;
207+ RCC_OscInitStruct .PLL2 .PLLState = RCC_PLL_NONE ;
208+ RCC_OscInitStruct .PLL3 .PLLState = RCC_PLL_NONE ;
209+ RCC_OscInitStruct .PLL4 .PLLState = RCC_PLL_NONE ;
210+ if (HAL_RCC_OscConfig (& RCC_OscInitStruct ) != HAL_OK ) {
211+ Error_Handler ();
212+ }
213+
214+ /* Wait HSE stabilization time before its selection as PLL source. */
215+ HAL_Delay (HSE_STARTUP_TIMEOUT );
216+
217+ /** Get current CPU/System buses clocks configuration and if necessary switch
218+ to intermediate HSI clock to ensure target clock can be set
219+ */
220+ HAL_RCC_GetClockConfig (& RCC_ClkInitStruct );
221+ if ((RCC_ClkInitStruct .CPUCLKSource == RCC_CPUCLKSOURCE_IC1 ) ||
222+ (RCC_ClkInitStruct .SYSCLKSource == RCC_SYSCLKSOURCE_IC2_IC6_IC11 )) {
223+ RCC_ClkInitStruct .ClockType = (RCC_CLOCKTYPE_CPUCLK | RCC_CLOCKTYPE_SYSCLK );
224+ RCC_ClkInitStruct .CPUCLKSource = RCC_CPUCLKSOURCE_HSI ;
225+ RCC_ClkInitStruct .SYSCLKSource = RCC_SYSCLKSOURCE_HSI ;
226+ if (HAL_RCC_ClockConfig (& RCC_ClkInitStruct ) != HAL_OK ) {
227+ /* Initialization Error */
228+ Error_Handler ();
229+ }
230+ }
231+
232+ /** Initializes the RCC Oscillators according to the specified parameters
233+ * in the RCC_OscInitTypeDef structure.
234+ */
235+ RCC_OscInitStruct .OscillatorType = RCC_OSCILLATORTYPE_HSE ;
236+ RCC_OscInitStruct .HSEState = RCC_HSE_ON ;
237+ RCC_OscInitStruct .PLL1 .PLLState = RCC_PLL_ON ;
238+ RCC_OscInitStruct .PLL1 .PLLSource = RCC_PLLSOURCE_HSE ;
239+ RCC_OscInitStruct .PLL1 .PLLM = 1 ;
240+ RCC_OscInitStruct .PLL1 .PLLN = 50 ;
241+ RCC_OscInitStruct .PLL1 .PLLFractional = 0 ;
242+ RCC_OscInitStruct .PLL1 .PLLP1 = 1 ;
243+ RCC_OscInitStruct .PLL1 .PLLP2 = 1 ;
244+ RCC_OscInitStruct .PLL2 .PLLState = RCC_PLL_NONE ;
245+ RCC_OscInitStruct .PLL3 .PLLState = RCC_PLL_NONE ;
246+ RCC_OscInitStruct .PLL4 .PLLState = RCC_PLL_NONE ;
247+ if (HAL_RCC_OscConfig (& RCC_OscInitStruct ) != HAL_OK ) {
248+ Error_Handler ();
249+ }
250+
251+ /** Initializes the CPU, AHB and APB buses clocks
252+ */
253+ RCC_ClkInitStruct .ClockType = RCC_CLOCKTYPE_CPUCLK | RCC_CLOCKTYPE_HCLK
254+ | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1
255+ | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK5
256+ | RCC_CLOCKTYPE_PCLK4 ;
257+ RCC_ClkInitStruct .CPUCLKSource = RCC_CPUCLKSOURCE_IC1 ;
258+ RCC_ClkInitStruct .SYSCLKSource = RCC_SYSCLKSOURCE_IC2_IC6_IC11 ;
259+ RCC_ClkInitStruct .AHBCLKDivider = RCC_HCLK_DIV2 ;
260+ RCC_ClkInitStruct .APB1CLKDivider = RCC_APB1_DIV1 ;
261+ RCC_ClkInitStruct .APB2CLKDivider = RCC_APB2_DIV1 ;
262+ RCC_ClkInitStruct .APB4CLKDivider = RCC_APB4_DIV1 ;
263+ RCC_ClkInitStruct .APB5CLKDivider = RCC_APB5_DIV1 ;
264+ RCC_ClkInitStruct .IC1Selection .ClockSelection = RCC_ICCLKSOURCE_PLL1 ;
265+ RCC_ClkInitStruct .IC1Selection .ClockDivider = 3 ;
266+ RCC_ClkInitStruct .IC2Selection .ClockSelection = RCC_ICCLKSOURCE_PLL1 ;
267+ RCC_ClkInitStruct .IC2Selection .ClockDivider = 6 ;
268+ RCC_ClkInitStruct .IC6Selection .ClockSelection = RCC_ICCLKSOURCE_PLL1 ;
269+ RCC_ClkInitStruct .IC6Selection .ClockDivider = 4 ;
270+ RCC_ClkInitStruct .IC11Selection .ClockSelection = RCC_ICCLKSOURCE_PLL1 ;
271+ RCC_ClkInitStruct .IC11Selection .ClockDivider = 3 ;
272+
273+ if (HAL_RCC_ClockConfig (& RCC_ClkInitStruct ) != HAL_OK ) {
274+ Error_Handler ();
275+ }
276+
277+ __HAL_RCC_AXISRAM3_MEM_CLK_ENABLE ();
278+ __HAL_RCC_AXISRAM4_MEM_CLK_ENABLE ();
279+ __HAL_RCC_AXISRAM5_MEM_CLK_ENABLE ();
280+ __HAL_RCC_AXISRAM6_MEM_CLK_ENABLE ();
281+ __HAL_RCC_AHBSRAM1_MEM_CLK_ENABLE ();
282+ __HAL_RCC_AHBSRAM2_MEM_CLK_ENABLE ();
283+ __HAL_RCC_BKPSRAM_MEM_CLK_ENABLE ();
284+ __HAL_RCC_FLEXRAM_MEM_CLK_ENABLE ();
285+ __HAL_RCC_CACHEAXIRAM_MEM_CLK_ENABLE ();
286+ __HAL_RCC_VENCRAM_MEM_CLK_ENABLE ();
287+ }
189288#endif
190289
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