Added an example

Author: EngCake

src/example/Makefile

@@ -0,0 +1,9 @@
+# Makefile
+
+SIM=icarus
+TOPLEVEL_LANG = verilog
+VERILOG_SOURCES = $(shell pwd)/dff.sv
+TOPLEVEL = dff
+MODULE = test_dff
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

src/example/dff.sv

@@ -0,0 +1,14 @@
+// dff.sv
+
+`timescale 1us/1ns
+
+module dff (
+    output logic q,
+    input logic clk, d
+);
+
+always @(posedge clk) begin
+    q <= d;
+end
+
+endmodule

src/example/test_dff.py

@@ -0,0 +1,35 @@
+# test_dff.py
+
+import random
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.types import LogicArray
+
+@cocotb.test()
+async def dff_simple_test(dut):
+    """Test that d propagates to q"""
+
+    # Assert initial output is unknown
+    assert LogicArray(dut.q.value) == LogicArray("X")
+    # Set initial input value to prevent it from floating
+    dut.d.value = 0
+
+    clock = Clock(dut.clk, 10, units="us")  # Create a 10us period clock on port clk
+    # Start the clock. Start it low to avoid issues on the first RisingEdge
+    cocotb.start_soon(clock.start(start_high=False))
+
+    # Synchronize with the clock. This will regisiter the initial `d` value
+    await RisingEdge(dut.clk)
+    expected_val = 0  # Matches initial input value
+    for i in range(10):
+        val = random.randint(0, 1)
+        dut.d.value = val  # Assign the random value val to the input port d
+        await RisingEdge(dut.clk)
+        assert dut.q.value == expected_val, f"output q was incorrect on the {i}th cycle"
+        expected_val = val # Save random value for next RisingEdge
+
+    # Check the final input on the next clock
+    await RisingEdge(dut.clk)
+    assert dut.q.value == expected_val, "output q was incorrect on the last cycle"