[fw-isoldr] Added support for NAOMI cart ROM.

Also some NAOMI fixes for Dreamcast compatibility.

Author: DC-SWAT

firmware/isoldr/loader/gdc_syscall.s

@@ -197,7 +197,7 @@ gdc_redir_bc:
 	mov     #0, r6
 gdc_redir_c0:
 	mov     r7, r0
-	mov     #16, r1
+	mov     #17, r1
 	cmp/hi  r0, r1
 	bf      bad_syscall
 	mov.l   gdc_syscall, r1
@@ -273,7 +273,7 @@ gdcUnk1:
 	.long _gdcDummy
 gdGdcChangeDisc:
 	.long _gdGdcChangeDisc
-gdcUnk3:
-	.long _gdcDummy
+gdGdcCartRead:
+	.long _gdGdcCartRead
 gdcUnk4:
 	.long _gdcDummy

firmware/isoldr/loader/include/main.h

@@ -76,7 +76,12 @@ extern isoldr_info_t *IsoInfo;
 extern uint32 loader_size;
 extern uint32 loader_addr;
 extern uint32 loader_end;
+
+extern uint32 boot_stack;
+extern uint32 boot_sr;
+extern uint32 boot_vbr;
 extern void boot_stub(void *, uint32) __attribute__((noreturn));
+
 void setup_machine(void);
 void shutdown_machine(void);
 void setup_region(void);

firmware/isoldr/loader/include/syscalls.h

@@ -7,6 +7,7 @@
 #ifndef _SYSCALLS_H
 #define _SYSCALLS_H
 
+#include <sys/types.h>
 #include <arch/types.h>
 #include <dc/cdrom.h>
 
@@ -224,4 +225,11 @@ int sys_misc_init(void);
 
 void menu_exit(void);
 
+typedef struct gdc_cart_read_params {
+	uint32_t offset;  // absolete offset in dump 
+	void *dst_buf;    // pointer to destation buffer
+	uint32_t size;    // size in bytes
+	uint32_t type;    // reading type: 0 - PIO, 1 - DMA
+} gdc_cart_read_params_t;
+
 #endif

firmware/isoldr/loader/main.c

@@ -118,29 +118,59 @@ int main(int argc, char *argv[]) {
 		}
 	}
 
-	if((IsoInfo->boot_mode != BOOT_MODE_DIRECT) ||
-		((loader_end < CACHED_ADDR(IP_BIN_ADDR) ||
-			loader_addr > CACHED_ADDR(APP_BIN_ADDR)) &&
-		(malloc_heap_pos() < CACHED_ADDR(IP_BIN_ADDR) ||
-			malloc_heap_pos() > CACHED_ADDR(APP_BIN_ADDR)))
-	) {
-		printf("Loading IP.BIN...\n");
-
-		if(!Load_IPBin(IsoInfo->boot_mode == BOOT_MODE_DIRECT ? 1 : 0)) {
-			goto error;
+	if(IsoInfo->image_type == IMAGE_TYPE_ROM_NAOMI) {
+
+		/* Clear ROM DMA busy flag */
+		*((uint32_t *)NONCACHED_ADDR(0x0c0000ac)) = 0;
+
+		/* Set VBR address for IRQ vectors */
+		boot_vbr = CACHED_ADDR(0x0c000000);
+		LOGF("Setting VBR address to %08lx\n", boot_vbr);
+
+		/* Set stack pointer */
+		boot_stack = CACHED_ADDR(0x0cc00000);
+		LOGF("Setting stack pointer to %08lx\n", boot_stack);
+
+		/* Set SR value */
+		boot_sr = 0x60000101;
+		LOGF("Setting SR to %08lx\n", boot_sr);
+
+		uint8_t *dst = (uint8_t *) NONCACHED_ADDR(SYSCALLS_FW_ADDR);
+		uint8_t *src = (uint8_t *) IsoInfo->syscalls;
+		LOGF("Loading IRQ vectors from %08lx to %08lx %d bytes\n",
+			(uintptr_t)src, (uintptr_t)dst, 0x4f00);
+		memcpy(dst, src, 0x4f00);
+
+		dst = (uint8_t *) NONCACHED_ADDR(0x0c018000);
+		src = (uint8_t *) IsoInfo->syscalls + 0x4f00;
+		LOGF("Loading IRQ handlers from %08lx to %08lx %d bytes\n",
+			(uintptr_t)src, (uintptr_t)dst, 0x7000);
+		memcpy(dst, src, 0x7000);
+	}
+	else {
+		if((IsoInfo->boot_mode != BOOT_MODE_DIRECT) ||
+			((loader_end < CACHED_ADDR(IP_BIN_ADDR) ||
+				loader_addr > CACHED_ADDR(APP_BIN_ADDR)) &&
+			(malloc_heap_pos() < CACHED_ADDR(IP_BIN_ADDR) ||
+				malloc_heap_pos() > CACHED_ADDR(APP_BIN_ADDR)))
+		) {
+			printf("Loading IP.BIN...\n");
+
+			if(!Load_IPBin(IsoInfo->boot_mode == BOOT_MODE_DIRECT ? 1 : 0)) {
+				goto error;
+			}
+		}
+		if(IsoInfo->exec.type != BIN_TYPE_KOS) {
+			/* Patch GDC driver entry */
+			gdc_syscall_patch();
 		}
-	}
-
-	if(IsoInfo->exec.type != BIN_TYPE_KOS) {
-		/* Patch GDC driver entry */
-		gdc_syscall_patch();
-	}
 
-	if(!is_dreamcast() && IsoInfo->exec.type == BIN_TYPE_KATANA) {
-		argc = patch_memory(0xff800030, (uint32)(&IsoInfo->cdda_offset[0]), 0);
-		LOGF("Patch GPIO register: %d\n", argc);
-		argc = patch_memory(0xffe80000, (uint32)(&IsoInfo->cdda_offset[1]), 0);
-		LOGF("Patch SCIF register: %d\n", argc);
+		if(!is_dreamcast() && IsoInfo->exec.type == BIN_TYPE_KATANA) {
+			/* Patch GPIO register to prevent cable detection */
+			argc = patch_memory(0xff800030,
+				IsoInfo->cdda_offset[(sizeof(IsoInfo->cdda_offset) / 4) - 1], 0);
+			LOGF("Patch GPIO register: %d\n", argc);
+		}
 	}
 
 #ifdef HAVE_EXPT
@@ -151,7 +181,7 @@ int main(int argc, char *argv[]) {
 #endif
 
 #ifdef HAVE_EXT_SYSCALLS
-	if(IsoInfo->syscalls) {
+	if(IsoInfo->syscalls && IsoInfo->image_type != IMAGE_TYPE_ROM_NAOMI) {
 		printf("Loading syscalls...\n");
 		Load_Syscalls();
 	}

firmware/isoldr/loader/reader.c

@@ -303,6 +303,7 @@ int ReadSectors(uint8 *buf, int sec, int num, fs_callback_f *cb) {
 			break;
 		}
 		case ISOFS_IMAGE_TYPE_ISO:
+		case IMAGE_TYPE_ROM_NAOMI:
 		default:
 		{
 			size_t offset = (sec - IsoInfo->track_lba[0]) * IsoInfo->sector_size;

firmware/isoldr/loader/startup.s

@@ -22,6 +22,9 @@
     .globl      _bios_patch_end
     .globl      _boot_stub
     .globl      _boot_stub_len
+    .globl      _boot_stack
+    .globl      _boot_sr
+    .globl      _boot_vbr
 
     .text
 start:
@@ -110,14 +113,17 @@ _bios_patch_end:
 _boot_stub:
     ! Set up some registers we will need to deal with later...
     mov         r4, r14
-    mov.l       newr15, r15
+    mov.l       newr15, r0
+    mov.l       @r0, r15
     ldc         r14, spc
     mov.l       newgbr, r0
     mov.l       ccr_addr, r3
     ldc         r0, gbr
     mov.l       newvbr, r1
+    mov.l       @r1, r1
     mov.w       ccr_data, r2
     mov.l       newsr, r4
+    mov.l       @r4, r4
     ldc         r1, vbr
     mov.l       newfpscr, r5
     ldc         r4, sr
@@ -154,14 +160,20 @@ ccr_data:
     .align     4
 ccr_addr:
     .long       0xff00001c
-newr15:
+_boot_stack:
     .long       0x8c00f400          ! r15
+newr15:
+    .long       _boot_stack
 newgbr:
     .long       0x8c000000          ! gbr
-newvbr:
+_boot_vbr:
     .long       0x8c00f400          ! vbr
-newsr:
+newvbr:
+    .long       _boot_vbr
+_boot_sr:
     .long       0x700000f0          ! sr
+newsr:
+    .long       _boot_sr
 newfpscr:
     .long       0x00040001          ! fpscr
 startaddr:

firmware/isoldr/loader/syscalls.c

@@ -744,8 +744,9 @@ static int init_cmd() {
 #endif
 
 	if(!is_dreamcast() && IsoInfo->exec.type == BIN_TYPE_KATANA) {
-		patch_memory(0xff800030, (uint32)(&IsoInfo->cdda_offset[0]), 5 << 20);
-		patch_memory(0xffe80000, (uint32)(&IsoInfo->cdda_offset[1]), 0);
+		/* Patch GPIO register to prevent cable detection */
+		patch_memory(0xff800030,
+			IsoInfo->cdda_offset[(sizeof(IsoInfo->cdda_offset) / 4) - 1], 5 << 20);
 	}
 	return CMD_STAT_COMPLETED;
 }
@@ -1396,6 +1397,24 @@ void gdGdcChangeDisc(int disc_num) {
 #endif
 }
 
+void gdGdcCartRead(gdc_cart_read_params_t *params) {
+	LOGFF("offset=%d dst=%08lx size=%d type=%d\n",
+		params->offset, (uint32)params->dst_buf,
+		params->size, params->type);
+
+	if(params->type) {
+		fs_enable_dma(FS_DMA_SHARED);
+	}
+	else {
+		fs_enable_dma(FS_DMA_DISABLED);
+	}
+
+	/* TODO: Async DMA support */
+	ReadSectors(params->dst_buf,
+		params->offset / IsoInfo->sector_size,
+		params->size / IsoInfo->sector_size, NULL);
+}
+
 void gdcDummy(int gd_chn, int *arg2) {
 	LOGFF("%d 0x%08lx 0x%08lx\n", gd_chn, arg2[0], arg2[1]);
 	(void)gd_chn;