Make wiring up ports common code and fix invert case

Author: robtaylor

chipflow_lib/platforms/sim.py

@@ -73,7 +73,8 @@ def instantiate_ports(self, m: Module):
         for component, iface in pinlock.port_map.items():
             for k, v in iface.items():
                 for name, port in v.items():
-                    self._ports[port.port_name] = io.SimulationPort(port.direction, port.width, invert=port.invert, name=f"{component}-{name}")
+                   invert = port.invert if port.invert else False
+                   self._ports[port.port_name] = io.SimulationPort(port.direction, port.width, invert=invert, name=f"{component}-{name}")
 
         for clock, name in self._config["chipflow"]["clocks"].items():
             if name not in pinlock.package.clocks: