chore: Fix some lint warnings

Author: robtaylor

chipflow_lib/platforms/sim.py

@@ -68,7 +68,7 @@ def add_monitor(self, inst_type, iface):
             box += '  wire width 1 input 0 \\clk\n'
             for i, ((field_name,), _, field) in enumerate(iface.signature.flatten(iface)):
                 field_width = Shape.cast(field.shape()).width
-                box += f'  wire width {field_width} input {i+1} \\{field_name}\n'
+                box += f'  wire width {field_width} input {i + 1} \\{field_name}\n'
             box += 'end\n\n'
             self.sim_boxes[inst_type] = box
         return Instance(inst_type, **conns)

chipflow_lib/software/soft_gen.py

@@ -51,9 +51,9 @@ def soc_h(self):
             result += f'#define puts(x) uart_puts({uart}, x)\n'
             result += f'#define puthex(x) uart_puthex({uart}, x)\n'
         else:
-            result += f'#define putc(x) do {{ (void)x; }} while(0) \n'
-            result += f'#define puts(x) do {{ (void)x; }} while(0)\n'
-            result += f'#define puthex(x) do {{ (void)x; }} while(0)\n'
+            result += '#define putc(x) do {{ (void)x; }} while(0)\n'
+            result += '#define puts(x) do {{ (void)x; }} while(0)\n'
+            result += '#define puthex(x) do {{ (void)x; }} while(0)\n'
 
         result += "#endif\n"
         return result
@@ -70,7 +70,7 @@ def start(self):
 
 # zero-initialize register file
 addi x1, zero, 0
-li x2, 0x{self.ram_start+self.ram_size:08x} # Top of stack
+li x2, 0x{self.ram_start + self.ram_size:08x} # Top of stack
 addi x3, zero, 0
 addi x4, zero, 0
 addi x5, zero, 0