tests: Update tests for pin-lock functionality

Author: robtaylor

tests/fixtures/chipflow-flexic.toml

@@ -0,0 +1,25 @@
+[chipflow]
+project_name = "proj-name"
+
+[chipflow.steps]
+silicon = "chipflow_lib.steps.silicon:SiliconStep"
+
+[chipflow.silicon]
+process = "ihp_sg13g2"
+package = "pga144"
+
+[chipflow.clocks]
+default = 'sys_clk'
+
+[chipflow.resets]
+default = 'sys_rst_n'
+
+[chipflow.silicon.pads]
+sys_clk     = { type = "clk", loc = "N3" }
+sys_rst_n    = { type = "i",   loc = "N4" }
+
+[chipflow.silicon.power]
+vss         = { loc = "N1" }
+vssio       = { loc = "N5" }
+vddio       = { loc = "N6" }
+vdd         = { loc = "N7" }

tests/fixtures/mock.toml

@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: BSD-2-Clause
+from amaranth import Module
+from amaranth.lib import wiring
+from amaranth.lib.wiring import In, Out
+
+from chipflow_lib.platforms import InputPinSignature, OutputPinSignature, BidirPinSignature
+
+__all__ = ["MockTop"]
+
+TestSignature1 = wiring.Signature({
+    "a": In(InputPinSignature(1)),
+    "b": In(InputPinSignature(5)),
+    "c": Out(OutputPinSignature(1)),
+    "d": Out(OutputPinSignature(10)),
+    "e": In(BidirPinSignature(1)),
+    "f": In(BidirPinSignature(7)),
+})
+
+TestSignature2 = wiring.Signature({
+    "a": Out(OutputPinSignature(1)),
+    "b": Out(OutputPinSignature(5)),
+    "c": In(InputPinSignature(1)),
+    "d": In(InputPinSignature(10)),
+    "e": Out(BidirPinSignature(1)),
+    "f": Out(BidirPinSignature(7)),
+})
+
+
+# ---------
+
+class MockTop(wiring.Component):
+    def __init__(self):
+        # Top level interfaces
+
+        interfaces = {
+            "test1" : Out(TestSignature1),
+            "test2": Out(TestSignature2)
+        }
+
+        super().__init__(interfaces)
+
+    def elaborate(self, platform):
+        m = Module()
+        for inpin, outpin in zip(self.test1.members, self.test2.members):
+            m.d.comb += inpin.eq(outpin)
+ 
+        return m

tests/fixtures/mock_top.py

@@ -2,10 +2,11 @@
 # SPDX-License-Identifier: BSD-2-Clause
 
 import os
-
 import unittest
+
+import tomli 
+
 from amaranth import *
-from amaranth.hdl import Fragment
 from amaranth.hdl._ir import Design
 
 from chipflow_lib import ChipFlowError
@@ -15,19 +16,23 @@
 class SiliconPlatformTestCase(unittest.TestCase):
     def setUp(self):
         os.environ["CHIPFLOW_ROOT"] = os.path.dirname(os.path.dirname(__file__))
+        current_dir = os.path.dirname(__file__)
+        customer_config = f"{current_dir}/fixtures/mock.toml"
+        with open(customer_config, "rb") as f:
+            self.config = tomli.load(f)
 
     def test_sync_domain_works(self):
         m = Module()
         m.domains += ClockDomain("sync")
 
-        fragment = SiliconPlatform(pads={})._prepare(m)
+        fragment = SiliconPlatform(self.config)._prepare(m)
         self.assertIsInstance(fragment, Design)
 
     def test_subfragment_works(self):
         m = Module()
         m.submodules += Module()
 
-        fragment = SiliconPlatform(pads={})._prepare(m)
+        fragment = SiliconPlatform(self.config)._prepare(m)
         self.assertIsInstance(fragment, Design)
 
     def test_wrong_clock_domain_name(self):
@@ -37,4 +42,4 @@ def test_wrong_clock_domain_name(self):
         with self.assertRaisesRegex(
                 ChipFlowError,
                 r"^Only a single clock domain, called 'sync', may be used$"):
-            SiliconPlatform(pads={}).build(m)
+            SiliconPlatform(self.config).build(m)

tests/test_silicon_platform.py

@@ -1,11 +1,11 @@
 # SPDX-License-Identifier: BSD-2-Clause
-
 import io
 import json
 import os
 import tomli
 import unittest
 from contextlib import redirect_stdout
+from pprint import pformat
 from unittest.mock import patch
 
 from chipflow_lib.steps.silicon import SiliconStep
@@ -29,7 +29,7 @@ def json(self):
             "msg": "msg",
             "url": "https://example.com/build-url/",
             "name": "name",
-            "id": 123,
+            "id": "proj-name",
         }, 200)
 
     return MockResponse(None, 404)
@@ -41,9 +41,10 @@ def setUp(self):
         os.environ["CHIPFLOW_API_KEY_ID"] = "keyid"
         os.environ["CHIPFLOW_API_KEY_SECRET"] = "keysecret"
 
+    @patch('dotenv.load_dotenv')
     @patch('requests.post', side_effect=mocked_requests_post)
-    def test_submit_happy_path(self, mock_requests_post):
-        customer_config = f"{current_dir}/fixtures/chipflow-flexic.toml"
+    def test_submit_happy_path(self, mock_requests_post, mock_dotenv):
+        customer_config = f"{current_dir}/fixtures/mock.toml"
         with open(customer_config, "rb") as f:
             config_dict = tomli.load(f)
 
@@ -53,7 +54,7 @@ def test_submit_happy_path(self, mock_requests_post):
         with redirect_stdout(f):
             silicon_step.submit(current_dir + "/fixtures/mock.rtlil")
         output = f.getvalue()
-        assert 'msg (#123: name); https://example.com/build-url/' in output, "The printed output is correct."
+        assert 'msg (#proj-name: name); https://example.com/build-url/' in output, "The printed output is correct."
 
         args = mock_requests_post.call_args_list[0][0]
         kwargs = mock_requests_post.call_args_list[0][1]
@@ -63,7 +64,7 @@ def test_submit_happy_path(self, mock_requests_post):
         rtlil = files["rtlil"].read()
         assert args[0] == 'https://app.chipflow-infra.com/api/builds'
         assert kwargs["auth"] == ("keyid", "keysecret")
-        assert data["projectId"] == 123
+        assert data["projectId"] == 'proj-name'
         assert isinstance(data["name"], str), "Name is a string"
         assert list(config["dependency_versions"]) == [
             "python",
@@ -73,10 +74,10 @@ def test_submit_happy_path(self, mock_requests_post):
             "amaranth-orchard", "amaranth-vexriscv",
         ], "We have entries for the the dependency versions"
 
+        print(pformat(config))
         assert config["silicon"] == {
-            'process': 'customer1',
-            'pad_ring':
-            'cf20',
+            'process': 'ihp_sg13g2',
+            'package': 'pga144',
             'pads': {},
             'power': {
                 'vss': {'loc': 'N1'},
@@ -86,3 +87,5 @@ def test_submit_happy_path(self, mock_requests_post):
             }
         }
         assert rtlil == b"fake-rtlil", "The RTL file was passed through."
+
+        assert mock_dotenv.called

tests/test_silicon_step.py

@@ -0,0 +1,105 @@
+# SPDX-License-Identifier: BSD-2-Clause
+import itertools
+import logging
+import pytest #noqa 
+
+from pprint import pformat
+
+from amaranth.lib import io
+
+from chipflow_lib.platforms.utils import PinSignature, OutputPinSignature, InputPinSignature, BidirPinSignature, _PinAnnotation, _PinAnnotationModel
+from chipflow_lib.platforms.utils import PinList, _group_consecutive_items,_find_contiguous_sequence, _Side
+
+
+logger = logging.getLogger(__name__)
+
+
+def gen_quad_pins(width, height) -> PinList:
+    return sorted(
+            [e for e in itertools.product((_Side.N, _Side.S), range(width))] +
+            [e for e in itertools.product((_Side.W, _Side.E), range(height))]
+           )
+
+
+def test_group_consecutive_items_null():
+    ordering = gen_quad_pins(50,60)
+    pins = ordering.copy()
+    groups = _group_consecutive_items(pins,pins)
+    assert len(groups.keys()) == 1
+    assert len(ordering) in groups.keys()
+
+def test_group_consecutive_items_nonconsecutive():
+    ordering = gen_quad_pins(50,60)
+    pins = ordering[0:6] + ordering[7:70] + ordering[71:180] + ordering[181:]
+    logger.debug(f"{ordering} {pins}")
+    groups = _group_consecutive_items(ordering,pins)
+    logger.debug(f"\n{pformat(groups)}")
+    assert len(ordering) == 50*2 + 60*2
+    assert len(groups.keys()) == 4
+    assert sum(groups.keys()) == len(ordering) - 3
+    assert 6 in groups.keys()
+    assert 70 - 7 in groups.keys()
+    assert 180 - 71 in groups.keys()
+    assert len(ordering) -181 in groups.keys()
+
+def test_find_contiguous_sequence():
+    ordering = gen_quad_pins(50,60)
+    pins = ordering[0:6] + ordering[7:70] + ordering[71:180] + ordering[181:]
+    seq = _find_contiguous_sequence(ordering, pins, 120)
+    logger.debug(f"\n{pformat(seq)}")
+    logger.debug(f"{ordering[71:180] + ordering[181:191]}")
+    assert len(seq) == 120
+    assert seq == ordering[71:180] + ordering[181:192]
+
+
+def test_pin_signature():
+    sig_bidir = PinSignature(io.Direction.Bidir, width=8)
+    assert isinstance(sig_bidir, PinSignature)
+    assert sig_bidir._direction == io.Direction.Bidir
+    assert sig_bidir._width == 8
+    assert "o" in sig_bidir.members
+    assert "oe" in sig_bidir.members
+    assert "i" in sig_bidir.members
+
+    sig_output = OutputPinSignature(width=4)
+    assert isinstance(sig_output, PinSignature)
+    assert sig_output._direction == io.Direction.Output
+    assert sig_output._width == 4
+    assert "o" in sig_output.members
+    assert "oe" not in sig_output.members
+    assert "i" not in sig_output.members
+
+    sig_input = InputPinSignature(width=2)
+    assert isinstance(sig_input, PinSignature)
+    assert sig_input._direction == io.Direction.Input
+    assert sig_input._width == 2
+    assert "o" not in sig_input.members
+    assert "oe" not in sig_output.members
+    assert "i" in sig_input.members
+
+    sig_bidir_fn = BidirPinSignature(width=1)
+    assert isinstance(sig_bidir_fn, PinSignature)
+    assert sig_bidir_fn._direction == io.Direction.Bidir
+    assert sig_bidir_fn._width == 1
+    assert "o" in sig_bidir_fn.members
+    assert "oe" in sig_bidir_fn.members
+    assert "i" in sig_bidir_fn.members
+
+def test_pin_annotation_model():
+    model = _PinAnnotationModel(direction=io.Direction.Output, width=32)
+    assert model.direction == "o"
+    assert model.width == 32
+
+def test_pin_annotation():
+    annotation = _PinAnnotation(direction=io.Direction.Input, width=16)
+    assert isinstance(annotation, _PinAnnotation)
+    assert annotation.model.direction == "i"
+    assert annotation.model.width == 16
+
+def test_pin_annotation_as_json():
+    annotation = _PinAnnotation(direction=io.Direction.Bidir, width=8)
+    json_output = annotation.as_json()
+    print(f"json_output: {json_output}") # Debug print using print()
+    assert isinstance(json_output, dict)
+    assert json_output["direction"] == "io"
+    assert json_output["width"] == 8