wip

Author: robtaylor

chipflow_lib/platforms/_utils.py

@@ -172,14 +172,22 @@ def _to_set(self) -> Set[Pin]:
                set([self.core_clock, self.core_reset, self.core_heartbeat]) | \
                self.core_jtag._to_set()
 
+class PadPowerDomain(pydantic.BaseModel):
+    io: str
+    internal: str
 
-class Port(AppResponseModel):
+class PadPowerDomains(StrEnum):
+    IO = 'io'
+    INTERNAL = 'internal'
+
+class PortModel(AppResponseModel):
+    "Configuration information for a platform port"
     type: str
     pins: List[Pin] | None  # None implies must be allocated at end
     port_name: str
     iomodel: IOModel
     power_allocation: Dict[InterfacePowerDomainName, PowerDomainName] = {}
-    power_domain: Annotated[Optional[str], OmitIfNone()] = None
+    pad_power_domains: Annotated[Optional[PadPowerDomain, OmitIfNone()]] = None
 
     def model_post_init(self, __context):
         logger.debug(f"Instantiating port {self.port_name}: {self}")
@@ -219,7 +227,7 @@ def interface_power_domains(self) -> List[str]:
             return []
 
 
-Interface = OrderedDict[str, Port]
+Interface = OrderedDict[str, PortModel]
 Component = OrderedDict[str, Interface]
 AllocateFunc = Callable[[PinSet, int], PinList]
 
@@ -235,7 +243,7 @@ def create_ports(name: str, member: Dict[str, Any], port_name: str) -> Interface
        and IO_ANNOTATION_SCHEMA in member['annotations']:
         model:IOModel = member['annotations'][IO_ANNOTATION_SCHEMA]
         logger.debug(f"matched IOSignature {model}")
-        pin_map[name] = Port(type='io', port_name=port_name, iomodel=model, pins=None)
+        pin_map[name] = PortModel(type='io', port_name=port_name, iomodel=model, pins=None)
         logger.debug(f"added '{name}':{pin_map[name]} to pin_map")
         return pin_map
     elif member['type'] == 'interface':
@@ -246,10 +254,10 @@ def create_ports(name: str, member: Dict[str, Any], port_name: str) -> Interface
             logger.debug(f"{pin_map},{_map}")
         return pin_map
     elif member['type'] == 'port':
-        logger.warning(f"Port '{name}' has no IOSignature, pin allocation likely to be wrong")
+        logger.warning(f"PortModel '{name}' has no IOSignature, pin allocation likely to be wrong")
         width = member['width']
         model = IOModel(width=int(width), direction=io.Direction(member['dir']))
-        pin_map[name] = Port(type='io', port_name=port_name, iomodel=model, pins=None)
+        pin_map[name] = PortModel(type='io', port_name=port_name, iomodel=model, pins=None)
         logger.debug(f"added '{name}':{pin_map[name]} to pin_map")
         return pin_map
     else:
@@ -267,7 +275,7 @@ def get_ports(self, component: str, interface: str) -> Interface:
             raise KeyError(f"'{component}' not found in {self}")
         return self.ports[component][interface]
 
-    def get_clocks(self) -> List[Port]:
+    def get_clocks(self) -> List[PortModel]:
         ret = []
         for n, c in self.ports.items():
             for cn, i in c.items():
@@ -276,7 +284,7 @@ def get_clocks(self) -> List[Port]:
                         ret.append(p)
         return ret
 
-    def get_resets(self) -> List[Port]:
+    def get_resets(self) -> List[PortModel]:
         ret = []
         for n, c in self.ports.items():
             for cn, i in c.items():
@@ -285,7 +293,7 @@ def get_resets(self) -> List[Port]:
                         ret.append(p)
         return ret
 
-    def add_port(self, component: str, interface: str, port_name: str, port: Port):
+    def add_port(self, component: str, interface: str, port_name: str, port: PortModel):
         "Internally used by a `PackageDef`"
         if component not in self.ports:
             self.ports[component] = Component()
@@ -333,15 +341,15 @@ def create_power_ports(self, component, interface):
         for ipd, ppd in power_allocation.items():
             prefix = f"_power_{ipd}_{ppd}"
             power_port = prefix + "_vdd"
-            power_domain = f"{ppd}"
+            pad_power_domain = f"{ppd}"
             if power_port not in self.ports[component][interface]:
-                self.ports[component][interface][power_port] = Port(type='power', pins=None, port_name=power_port,
-                        power_domain=power_domain, iomodel=IOModel(width=1, direction=io.Direction.Input))
+                self.ports[component][interface][power_port] = PortModel(type='power', pins=None, port_name=power_port,
+                        pad_power_domain=pad_power_domain, iomodel=IOModel(width=1, direction=io.Direction.Input))
 
             power_port = prefix + "_vss"
             if power_port not in self.ports[component][interface]:
-                self.ports[component][interface][power_port] = Port(type='power', pins=None, port_name=power_port,
-                        power_domain=power_domain, iomodel=IOModel(width=1, direction=io.Direction.Input))
+                self.ports[component][interface][power_port] = PortModel(type='power', pins=None, port_name=power_port,
+                        pad_power_domain=pad_power_domain, iomodel=IOModel(width=1, direction=io.Direction.Input))
 
     def check_core_power(self, core_domain, _type, voltage):
         if core_domain not in self.pad_power_domains:
@@ -811,13 +819,13 @@ def _allocate_bringup(self, config: 'Config') -> Component:
         cds = set(config.chipflow.clock_domains) if config.chipflow.clock_domains else set()
         cds.discard('sync')
 
-        d: Interface = { 'sync-clk': Port(type='clock',
+        d: Interface = { 'sync-clk': PortModel(type='clock',
                                           pins=[self.bringup_pins.core_clock],
                                           port_name='sync-clk',
                                           iomodel=IOModel(width=1, direction=io.Direction.Input,
                                                           clock_domain="sync")
                                       ),
-                          'sync-rst_n': Port(type='reset',
+                          'sync-rst_n': PortModel(type='reset',
                                            pins=[self.bringup_pins.core_reset],
                                            port_name='sync-rst_n',
                                            iomodel=IOModel(width=1, direction=io.Direction.Input, clock_domain="sync",
@@ -830,23 +838,23 @@ def _allocate_bringup(self, config: 'Config') -> Component:
             vdd_pins.append(pp.ground)
             vss_pins.append(pp.power)
 
-        d |= {'vdd' : Port(type='power',
+        d |= {'vdd' : PortModel(type='vdd',
                            pins=vdd_pins,
                            port_name="vdd-core",
-                           power_domain="_core",
+                           pad_power_domains="_core",
                            iomodel=IOModel(width=len(vdd_pins), direction=io.Direction.Input)),
-              'vss' : Port(type='power',
+              'vss' : PortModel(type='vss',
                            pins=vss_pins,
                            port_name="vss-core",
-                           power_domain="_core",
+                           pad_power_domains="_core",
                            iomodel=IOModel(width=len(vss_pins), direction=io.Direction.Input))
               }
 
 
         assert config.chipflow.silicon
         if config.chipflow.silicon.debug and \
            config.chipflow.silicon.debug['heartbeat']:
-            d['heartbeat'] = Port(type='heartbeat',
+            d['heartbeat'] = PortModel(type='heartbeat',
                                   pins=[self.bringup_pins.core_heartbeat],
                                   port_name='heartbeat',
                                   iomodel=IOModel(width=1, direction=io.Direction.Output, clock_domain="sync")