Reduce API surface

Author: robtaylor

chipflow_lib/__init__.py

@@ -15,6 +15,7 @@
 
 __version__ = importlib.metadata.version("chipflow_lib")
 
+
 logger = logging.getLogger(__name__)
 
 class ChipFlowError(Exception):

chipflow_lib/pin_lock.py renamed to chipflow_lib/_pin_lock.py

@@ -14,7 +14,7 @@
     _get_cls_by_reference,
     _parse_config,
 )
-from .pin_lock import PinCommand
+from ._pin_lock import PinCommand
 
 class UnexpectedError(ChipFlowError):
     pass

chipflow_lib/cli.py

@@ -8,7 +8,7 @@
 
 from .silicon import SiliconPlatformPort, SiliconPlatform
 from .sim import SimPlatform
-from .utils import (
+from ._utils import (
         IO_ANNOTATION_SCHEMA, IOSignature, IOModel, IODriveMode, IOTripPoint, IOModelOptions,
         OutputIOSignature, InputIOSignature, BidirIOSignature,
         )

chipflow_lib/platforms/__init__.py

@@ -1,6 +1,6 @@
 from .silicon import *
 from .sim import *
-from .utils import *
+from ._utils import *
 from ._packages import *
 __all__ = ['IO_ANNOTATION_SCHEMA', 'IOSignature', 'IOModel',
            'OutputIOSignature', 'InputIOSignature', 'BidirIOSignature',

chipflow_lib/platforms/_internal.py

@@ -1,6 +1,6 @@
 from typing import List, NamedTuple, Optional, Literal
 
-from .utils import Voltage, PowerPins, LinearAllocPackageDef, BringupPins
+from ._utils import Voltage, PowerPins, LinearAllocPackageDef, BringupPins
 
 class OFPin(NamedTuple):
     pin: int

chipflow_lib/platforms/_openframe.py

@@ -1,4 +1,4 @@
-from .utils import QuadPackageDef, BareDiePackageDef, Package
+from ._utils import QuadPackageDef, BareDiePackageDef, Package
 from ._openframe import OpenframePackageDef
 
 # Add any new package types to both PACKAGE_DEFINITIONS and the PackageDef union

chipflow_lib/platforms/_packages.py

@@ -21,7 +21,7 @@
 from amaranth.hdl._ir import PortDirection
 
 from .. import ChipFlowError
-from .utils import load_pinlock, PortDesc, Pin, IOModel, IODriveMode, IOTripPoint, Process
+from ._utils import load_pinlock, PortDesc, Pin, IOModel, IODriveMode, IOTripPoint, Process
 
 if TYPE_CHECKING:
     from ..config_models import Config

chipflow_lib/platforms/utils.py renamed to chipflow_lib/platforms/_utils.py

@@ -11,7 +11,7 @@
 from amaranth.hdl._ir import PortDirection
 from amaranth.lib.cdc import FFSynchronizer
 
-from .utils import load_pinlock
+from ._utils import load_pinlock
 
 
 __all__ = ["SimPlatform"]