wip

Author: robtaylor

chipflow_lib/pin_lock.py

@@ -10,7 +10,7 @@
 from chipflow_lib.platforms import (
         PACKAGE_DEFINITIONS,
         PIN_ANNOTATION_SCHEMA,
-        top_interfaces,
+        top_components,
         LockFile,
         Package,
         PortMap,
@@ -22,80 +22,13 @@
 logger = logging.getLogger(__name__)
 
 
-def count_member_pins(name: str, member: Dict[str, Any]) -> int:
-    "Counts the pins from amaranth metadata"
-    logger.debug(
-        f"count_pins {name} {member['type']} "
-        f"{member['annotations'] if 'annotations' in member else 'no annotations'}"
-    )
-    if member['type'] == 'interface' and 'annotations' in member \
-       and PIN_ANNOTATION_SCHEMA in member['annotations']:
-        return member['annotations'][PIN_ANNOTATION_SCHEMA]['width']
-    elif member['type'] == 'interface':
-        width = 0
-        for n, v in member['members'].items():
-            width += count_member_pins('_'.join([name, n]), v)
-        return width
-    elif member['type'] == 'port':
-        return member['width']
-
-
-def allocate_pins(name: str, member: Dict[str, Any], pins: List[str], port_name: str = None) -> Tuple[Dict[str, Port], List[str]]:
-    "Allocate pins based of Amaranth member metadata"
-
-    if port_name is None:
-        port_name = name
-
-    pin_map = {}
-
-    logger.debug(f"allocate_pins: name={name}, pins={pins}")
-    logger.debug(f"member={pformat(member)}")
-
-    if member['type'] == 'interface' and 'annotations' in member \
-       and PIN_ANNOTATION_SCHEMA in member['annotations']:
-        logger.debug("matched IOSignature {sig}")
-        sig = member['annotations'][PIN_ANNOTATION_SCHEMA]
-        logger.debug(f"matched PinSignature {sig}")
-        name = name
-        width = sig['width']
-        options = sig['options']
-        pin_map[name] = {'pins': pins[0:width],
-                         'direction': sig['direction'],
-                         'type': 'io',
-                         'port_name': port_name,
-                         'options': options}
-        logger.debug(f"added '{name}':{pin_map[name]} to pin_map")
-        return pin_map, pins[width:]
-    elif member['type'] == 'interface':
-        for k, v in member['members'].items():
-            port_name = '_'.join([name, k])
-            _map, pins = allocate_pins(k, v, pins, port_name=port_name)
-            pin_map |= _map
-            logger.debug(f"{pin_map},{_map}")
-        return pin_map, pins
-    elif member['type'] == 'port':
-        logger.warning(f"Port '{name}' has no IOSignature, pin allocation likely to be wrong")
-        width = member['width']
-        pin_map[name] = {'pins': pins[0:width],
-                              'direction': member['dir'],
-                              'type': 'io',
-                              'port_name': port_name
-                              }
-        logger.debug(f"added '{name}':{pin_map[name]} to pin_map")
-        return pin_map, pins[width:]
-    else:
-        logging.debug(f"Shouldnt get here. member = {member}")
-        assert False
-
-
 def lock_pins() -> None:
-    # Get the config as dict for backward compatibility with top_interfaces
+    # Get the config as dict for backward compatibility with top_components
     config_dict = _parse_config()
 
     # Parse with Pydantic for type checking and strong typing
     config_model = Config.model_validate(config_dict)
 
-    used_pins = set()
     oldlock = None
 
     chipflow_root = _ensure_chipflow_root()
@@ -111,9 +44,9 @@ def lock_pins() -> None:
 
     if package_name not in PACKAGE_DEFINITIONS:
         logger.debug(f"Package '{package_name} is unknown")
-    package_type = PACKAGE_DEFINITIONS[package_name]
 
-    package = Package(package_type=package_type)
+    # TODO, ugh, clean this up.
+    package = Package(package_type=PACKAGE_DEFINITIONS[package_name])
 
     # Initialize standard pins from package type
     package.initialize_from_package_type()
@@ -123,7 +56,6 @@ def lock_pins() -> None:
     silicon_config = getattr(config_model.chipflow.silicon, "pads", {})
     for k, v in silicon_config.items():
         pin = str(v.loc)
-        used_pins.add(pin)
 
         # Convert Pydantic model to dict for backward compatibility
         v_dict = {"type": v.type, "loc": v.loc}
@@ -146,39 +78,10 @@ def lock_pins() -> None:
 
     logger.debug(f"unallocated pins = {package_type.sortpins(unallocated)}")
 
-    # Use the raw dict for top_interfaces since it expects the legacy format
-    _, interfaces = top_interfaces(config_dict)
+    top = top_components(config_dict)
 
-    logger.debug(f"All interfaces:\n{pformat(interfaces)}")
-
-    port_map = PortMap({})
-    # we try to keep pins together for each interface
+    # Use the PackageDef to allocate the pins:
     for component, iface in interfaces.items():
-        for k, v in iface['interface']['members'].items():
-            logger.debug(f"Interface {component}.{k}:")
-            logger.debug(pformat(v))
-            width = count_member_pins(k, v)
-            logger.debug(f"  {k}: total {width} pins")
-            old_ports = oldlock.port_map.get_ports(component, k) if oldlock else None
-            if old_ports:
-                logger.debug(f"  {component}.{k} found in pins.lock, reusing")
-                logger.debug(pformat(old_ports))
-                old_width = sum([len(p.pins) for p in old_ports.values()])
-                if old_width != width:
-                    raise ChipFlowError(
-                        f"top level interface has changed size. "
-                        f"Old size = {old_width}, new size = {width}"
-                    )
-                port_map.add_ports(component, k, old_ports)
-            else:
-                pins = package_type.allocate(unallocated, width)
-                if len(pins) == 0:
-                    raise ChipFlowError("No pins were allocated by {package}")
-                logger.debug(f"allocated range: {pins}")
-                unallocated = unallocated - set(pins)
-                _map, _ = allocate_pins(k, v, pins)
-                port_map.add_ports(component, k, _map)
-
     newlock = LockFile(process=process,
                        package=package,
                        port_map=port_map,